Abstract: A temperature sensor for use in an infrared detector the temperature sensor comprising: a first resistor associated with a first thermal path having a first thermal conductivity between the first resistor and a substrate and a first temperature coefficient of resistance; a second resistor associated with a second thermal path having a second thermal conductivity between the second resistor and the substrate and a second temperature coefficient of resistance, and a measurement circuit responsive to changes in the resistance of the first and second resistors to estimate changes in temperature, and wherein at least one of (a) the first and second thermal conductivities are different or (b) the first and second temperature coefficients of resistance are different.

Abstract: The invention is directed to a multi-bit digital signal isolation system including a plurality of micro-transformers, each having a primary winding and a secondary winding, a transmitter circuit receiving a multi-bit signal and transmitting an encoded logic signal across the plurality of micro-transformers corresponding to the multi-bit signal, the primary winding of each micro-transformer receiving a signal corresponding to one of at least three possible states, and a receiver circuit receiving the encoded logic signal from the secondary windings of the plurality of transformers, decoding the encoded logic signal and reconstructing the received multi-bit signal based upon the decoded signal.

Abstract: A system and method provide for an adaptive median filter with edge protection and four line buffers to remove the impulse noise for a Bayer pattern image. The system and method separates the Bayer pattern image data into different channels by color and applies the adaptive median filter to remove the impulse noise on each channel. The adaptive median filter has five threshold values that may be modified to achieve different light condition response based on the detected noise level of the image. Thus, proper threshold values with better brightness response to the input pixels may be applied and impulse noise may be suppressed effectively, while preserving image details.

Abstract: Vertical mount packages and methods for making the same are disclosed. A method for manufacturing a vertical mount package includes providing a device substrate with a plurality of device regions on a front surface, and a plurality of through-wafer vias. MEMS devices or integrated circuits are formed or mounted onto the device regions. A capping substrate having recesses is mounted over the device substrate, enclosing the device regions within cavities defined by the recesses. A plurality of aligned through-wafer contacts extend through the capping substrate and the device substrate. The device substrate and capping substrate can be singulated by cutting through the aligned through-wafer contacts, with the severed through-wafer contacts forming vertical mount leads. A vertical mount package includes a device sealed between a device substrate and a capping substrate. At least of the side edges of the package includes exposed conductive elements for vertical mount leads.

Abstract: A system and method for implementing a differential signaling driver with a common-mode voltage not equal to one half the power supply voltage using voltage-mode techniques. Embodiments of the present invention maintain balanced impedance at the signal output. In an embodiment, a driver may have multiple operating modes for each potential supply voltage or common-mode voltage. In an embodiment, each potential mode may involve configuring the driver by activating or deactivating switches or resistors in the driver and each potential mode may have different resistor values.

Abstract: A method for measuring retained surface charges within a MEMS device includes performing an initial voltage sweep on the MEMS device, and recording the capacitance between a first and second electrode of the MEMS device. The method may then (1) apply a stress signal to the MEMS device that causes a first and/or second electrode within the MES device to retain a surface charge, and (2) perform at least one additional voltage sweep on the MEMS device. The method may record the capacitance during the additional voltage sweep(s), and calculate a C-V center voltage shift based upon the data obtained during the initial voltage sweep and additional voltage sweep. The voltage shift is representative of the retained surface charge.

Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.

Abstract: Apparatus and methods are disclosed related to using one or more field effect transistors as a resistor. One such apparatus can include a field effect transistor (FET), averaging resistors and a bidirectional current source. The averaging resistors can apply an average of a voltage at the source of the FET and a voltage at the drain of the FET to the gate of the field effect transistor. The bidirectional current source can turn the FET on and off. The FET can operate in the ohmic region when on. Such an apparatus can improve the linearity of the FET as a resistor, for example, at lower frequencies near or at direct current (DC). In some implementations, the apparatus can include one or more current sources to remove an offset introduced by the bidirectional current source at the source and/or the drain of the FET.

Abstract: A system provides for a serial transmitter with multiplexing and driving functionality that is combined into a single stage to increase the overall speed of the serial transmitter. The single stage includes a dynamic impedance that is configured in parallel with a multiplexing driver to reduce the input capacitance and set the correct output impedance. The single stage can be implemented as a stacked or cross-coupled XOR logic circuit or a stacked or cross-coupled multiplexer (“mux”) as the multiplexing driver. In an embodiment where a mux is used as the multiplexing driver, a clock can be injected into the mux driver to overcome inter-symbol interference.

Abstract: A voltage reference is produced from PTAT, CTAT, and nonlinear current components generated in isolation from each other and combined to create the voltage reference.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: A reference circuit for use with a charge redistribution analog to digital converter, having a capacitor array, the reference circuit comprising: an input for receiving a signal; an output for supplying a reference voltage to at least one capacitor of the charge redistribution capacitor array; a storage capacitor for storing the reference voltage; a voltage modification circuit for comparing the reference voltage stored on the storage capacitor with the reference signal, and based on the comparison to supply a correction so as to reduce a difference between the reference voltage and the reference signal, the correction being applied during a correction phase; and a first switch for selectively connecting the storage capacitor to the input during an acquisition phase.

Abstract: An infrared sensor, comprising at least one pixel comprising a first sensor and a second sensor, wherein the first and second sensors are dissimilar.

Abstract: A transconductance circuit that improves linearity and output current over a wider range of input voltages than prior designs. The transconductance circuit may include first and second sets of paired differential transistors. In each set, emitters of the paired transistors may be commonly coupled to corresponding nodes of a common impedance, and collectors may be coupled to output terminals of the transconductance circuit. The circuit may further include first and second sets of doublet differential transistor pairs, each doublet pair having transistors of different sizes. Each doublet pair may have current sources coupled between commonly coupled emitters and a source potential. Respective collectors for each doublet pair may be coupled to the output terminals of the transconductance circuit. A pair of voltage followers may be provided to replicate corresponding input voltages across corresponding bases of the differential transistor pairs and the doublet transistor pairs.

Abstract: A method and corresponding circuits for operating a parallel DMOS switch that includes a pair of P-type DMOS devices connected in series with each other and in parallel with a pair of N-type DMOS devices connected in series with each other. The method and circuits involve turning the switch on by applying gate signals to the DMOS device pairs which are generated using at least one source voltage of a DMOS device pair. The switch is turned off by setting the gate signals equal to the respective source voltages of the DMOS device pairs.

Abstract: A bi-directional switch circuit includes a pair of N-type MOS devices connected in series with a common source terminal, and a pair of P-type MOS devices connected in series with a common source terminal. The series connected N-type devices are connected in parallel with the series connected P-type devices in a configuration that includes a first input/output (I/O) point of the switch circuit being connected to a drain of a first one of the N-type devices and a drain of a first one of the P-type devices. The parallel configuration also includes a second I/O point of the switch circuit being connected to a drain of a second one of the N-type devices and a drain of a second one of the P-type devices.

Abstract: Apparatus and methods for reducing output noise of a signal channel are provided. In one embodiment, a signal channel includes an amplifier for amplifying an input signal to generate an amplified signal. The amplifier includes a bias circuit that controls a bias current of the amplifier based on a voltage across a biasing capacitor. The apparatus further includes a sampling circuit for sampling the amplified signal. The sampling circuit generates an output signal based on a difference between a first sample of the amplified signal taken at a first time instance and a second sample of the amplified signal taken at a second time instance. The bias circuit samples a bias voltage onto the biasing capacitor before the first time instance and holds the voltage across the biasing capacitor substantially constant between the first time instance and the second time instance to reduce noise of the output signal.

Abstract: In an embodiment, a primary charge pump and replica charge pump may be coupled to matching control mechanisms and loads. In an embodiment, the replica charge pump may produce an error current originating from charge pump timing mismatches in a steady locked loop state. The error current produced by the replica charge pump may be measured by a difference amplifier to adjust at least one current source to compensate for the error current originating from the timing mismatches. To adjust the current sources, the amplifier may cause the current source to produce an equal but opposite current to cancel the effects of the error current, resulting in a constant output voltage.

Abstract: The present invention relates to a driver circuit wherein upper and lower legs of a first driver comprise first and second sets of parellelly coupled semiconductor switches, respectively. A control circuit is configured to generate respective control signals for the first and second sets of parellelly coupled semiconductor switches to create a current path through the upper and lower legs during an overlap time period between state transitions of a driver output.

Abstract: Embodiments of the present invention may provide a power supply system that uses a capacitive voltage divider to selectively monitor various power supplies on an IC chip. The power supply system may sample a monitored power supply to a capacitor and select certain capacitors from a set of switched capacitors to divide down the sampled voltage. The resulting voltage may be compared to a voltage reference. Using different selections of switched capacitors, the monitored power supply may be compared for different voltage levels. The ratio of the sampling capacitor to the selected capacitors may determine a voltage level the comparator will trigger. Further, based on the monitored power supply level, the power supply system may turn on a switch between an external power supply and a regulated digital power supply to charge the regulated digital power supply while a main LDO is turned off.