Abstract: A voltage converter circuit can include a boost converter having a switching transistor and configured to receive an input voltage, produce an output voltage and selectively operate in one of a boost mode, a skip mode and a linear mode. In the boost and skip modes, the boost converter can switch on and off the switching transistor at a switching frequency to produce an output voltage at magnitudes greater than input voltage magnitudes. In the linear mode, the boost converter can turn off the switching transistor at all times to pass the input voltage unboosted to produce an output voltage at magnitudes less than input voltage magnitudes.

Abstract: Embodiments of the present invention may provide a power-gating switch circuit. The power-gating switch circuit may comprise a first switch to connect a power supply to a virtual power supply and a second switch to connect the power supply to the virtual power supply in parallel to the first switch. The first switch may have a higher impedance than the second switch. When a wake up signal is received, the first switch may be turned on first and the second switch may be turned on after the virtual power supply reaches a predetermined voltage level.

Abstract: A micromachining process forms a plurality of layers on a wafer. This plurality of layers includes both a support layer and a given layer. The process also forms a mask, with a mask hole, at least in part on the support layer. In this configuration, the support layer is positioned between the mask hole and the given layer, and longitudinally spaces the mask hole from the given layer. The process also etches a feature into the given layer through the mask hole.

Abstract: A method of forming a microphone forms a backplate, and a flexible diaphragm on at least a portion of a wet etch removable sacrificial layer. The method adds a wet etch resistant material, where a portion of the wet etch resistant material is positioned between the diaphragm and the backplate to support the diaphragm. Some of the wet etch resistant material is not positioned between the diaphragm and backplate. The method then removes the sacrificial material before removing any of the wet etch resistant material added during the prior noted act of adding. The wet etch resistant material then is removed substantially in its entirety after removing at least part of the sacrificial material.

Abstract: Apparatus and methods are also disclosed related to an oscillator that includes a switching network configured to tune a resonant frequency of a resonant circuit. One such apparatus includes a switching network having a circuit element, such as a capacitor, that can be selectively coupled to the resonant circuit by a switch, such as a field effect transistor. For instance, the switch can electrically couple to circuit element to the resonant circuit when on and not electrically couple the circuit element to the resonant circuit when off. An active circuit can assert a high impedance on an intermediate node between the switch and the circuit element when the switch is off.

Abstract: An amplifier circuit includes a first amplifier stage having a first output node; a second amplifier stage having a second output node; and a compensation block electrically coupled between the first and second output nodes. The compensation block has a compensation capacitor electrically coupled to the first node and electrically connectable to the second node, and has an impedance electrically connectable to the compensation capacitor. The compensation capacitor is electrically coupled via a switch to the impedance such that the compensation capacitor can contribute a zero to shunt branch formed by the compensation capacitor and impedance when the compensation capacitor is disconnected from the second node.

Abstract: An integrated circuit has a semiconductor die provided in a first IC layer and an inductor fabricated on a second IC layer. The inductor may have a winding and a magnetic core, which are oriented to conduct magnetic flux in a direction parallel to a surface of a semiconductor die. The semiconductor die may have active circuit components fabricated in a first layer of the die, provided under the inductor layer. The integrated circuit may include a flux conductor provided on a side of the die opposite the first layer. PCB connections to active elements on the semiconductor die may progress through the inductor layer as necessary.

Abstract: Embodiments of the present disclosure may provide a charge redistribution DAC with an on-chip reservoir capacitor to provide charges to the DAC in lieu of traditional external reference voltages. The DAC may include the on-chip reservoir capacitor having a first plate and a second plate, an array of DAC capacitors to generate a DAC output, and an array of switches controlled by a DAC input word to couple the DAC capacitors to the reservoir capacitor. The charge redistribution DAC may further comprise a first switch connecting the first plate to an external terminal for a first external reference voltage, and a second switch connecting the second plate to an external terminal for a second external reference voltage. One embodiment may provide an ADC that includes the charge redistribution DAC.

Abstract: Embodiments of the present invention may provide an integrated circuit that may comprise a first transistor to receive an input voltage signal at its gate and generate an output voltage signal at its drain. Further, the integrated circuit may comprise a second transistor to form an active load of the first transistor, the second transistor may have its drain and gate coupled to the drain of the first transistor. In addition, the integrated circuit may comprise a third transistor to form a current mirror with the second transistor, a fourth transistor to form an active load of the third transistor, and a fifth transistor to form a current mirror with the fourth transistor. The fifth transistor may be connected to the drain of the second transistor. The integrated circuit may form an amplifier and Gm stage of a reference buffer.

Abstract: A method of producing a MEMS device provides a MEMS apparatus having released structure. The MEMS apparatus is formed at least in part from an SOI wafer having a first layer, a second layer spaced from the first layer, and an insulator layer between the first layer and second layer. The first layer has a top surface, while the second layer has a bottom surface facing the top surface. After providing the MEMS apparatus, the method increases the roughness of at least the top surface of the first layer or the bottom surface of the second layer.

Abstract: Apparatus and methods reduce the likelihood of amplifier saturation due to propagated DC offsets, and reduce the recover from saturated stated when such saturation occurs. Advantageously, these attributes are beneficial for monitoring of bioelectric signals. A circuit uses an instrumentation amplifier connected as a high pass filter to attenuate large DC offsets and amplify small signals. The circuit can include an instrumentation amplifier electrically coupled with a first feedback circuit including at least one resistor and a second feedback circuit including an op-amp. The feedback circuit can also include a low-pass filter. The op-amp in the second feedback circuit can be configured as a non-inverting amplifier, an inverting amplifier, and/or an integrator circuit. Alternatively, the circuit can include an instrumentation amplifier with one feedback circuit including at least one resistor, and a coupling capacitor electrically coupled with a reference voltage.

Abstract: A field effect transistor having a drain, a gate and a source, where the drain and source are formed by semiconductor regions of a first type, and in which a further doped region is provided intermediate the gate and the drain. Field gradients around the drain are thereby reduced.

Abstract: Apparatuses are disclosed, such as those involving integrated circuit packaging. In one embodiment, a chip package includes: an encapsulation having a top surface and a bottom surface facing away from the top surface. The package further includes a leadframe including a plurality of leads. Each of the leads includes an exposed portion exposed through one of edges of the bottom surface of the encapsulation. The exposed portion has a length. At least one of exposed portions positioned along one of the edges of the bottom surface of the encapsulation has a length different from other exposed portions along the edge. The package can also include a dummy pad exposed through a corner of the bottom surface. The configuration can enhance solder joint reliability of the package when the package is attached to a printed circuit board.

Abstract: Backside recesses in a base member host components, such as sensors or circuits, to allow closer proximity and efficient use of the surface space and internal volume of the base member. Recesses may include covers, caps, filters and lenses, and may be in communication with circuits on the frontside of the base member, or with circuits on an active backside cap. An array of recessed components may a form complete, compact sensor system.

Abstract: An analog-to-digital converter system that includes a pipeline of successively-cascaded signal converters, each operating alternatively in a first circuit configuration and a second circuit configuration, an error estimator coupled to the pipeline to receive the digitized error for estimating an amplifier gain of the present signal converter stage, and a code aligner/corrector that temporally aligns and corrects the digital codes received from the successively-cascaded signal converters to provide a digital out of the ADC system.

Abstract: A method to adjust a waveform transmitted from a field device to overcome cable bandwidth limitations by passing data to be transmitted through a channel compensation device which pre-distorts data to be transmitted to compensate for the bandwidth limitations. The predistortion may make sure that there is a good quality signal received at the control end of the cable.

Abstract: Techniques to control a capacitive touch screen that decrease processing time and increase noise rejection. The techniques may include injecting a plurality of excitation signals having unique spectral profiles onto conductors of the capacitive touch screen, sampling signals returned from the screen, and determining a location of touch. The techniques may further include injecting a plurality of excitation signals having unique spectral profiles onto adjacent or non-adjacent conductors of the capacitive touch screen. The techniques may further include injecting a plurality of excitation signals having unique spectral profiles onto conductors of the capacitive touch screen in unequal measures. The techniques may also include mapping frequency characteristics of noise present on the capacitive touch screen.

Abstract: Techniques to provide bootstrap control of a CMOS transistor switch. The techniques may include driving a control terminal of a CMOS transistor switch to a first predetermined voltage to set the CMOS transistor switch to an off-state. The first predetermined voltage may be drained to a discharge voltage and the control terminal may be driven to a second predetermined voltage to set the CMOS transistor switch to an on-state. The control terminal may be driven to the first predetermined voltage to return the CMOS transistor switch to the off-state.

Abstract: A device and method for measuring active and reactive powers of an alternating current includes receiving a first signal representing a current and a second signal representing a voltage, in which the current includes a phase offset with respect to the voltage, calculating an active power and reactive power based on the first and second signals, and calibrating the calculated active and reactive powers with respect to the phase offset using first and second constants, in which the first and second constants respectively correspond to a sine value and a cosine value of the phase offset.

Abstract: As provided herein, in some embodiments, power consumption and/or chip area is reduced by bias circuits configured to provide bias conditions for more than one active circuit, thereby reducing the number of bias circuits in a design. Shared bias circuits may reduce the aggregate amount of on-chip area utilized by bias circuitry and may also reduce the total power consumption of a chip. Additionally and/or alternatively, bias circuits disclosed herein are configured to provide outputs that are less susceptible to changes in the voltage supply level. In particular, in some embodiments, bias circuits are configured to provide relatively constant bias conditions despite changes in the voltage supply level. In some embodiments, bias circuits are configured to provide bias conditions that compensate for perturbations caused by changes other inputs, in order to stabilize a particular operating point.