Abstract: Embodiments of the present invention provide an adaptive noise canceling system. The adaptive noise canceling system may be used in a handset to cancel background noise by generating an anti-noise signal. The adaptive noise canceling system may include first input to receive a first signal from a feedforward microphone; a second input to receive a second signal from an error microphone; a controller coupled to the inputs, the controller configured to adaptively generate an anti-noise signal according to the received signals, wherein the controller derives a profile of the anti-noise signal from the first signal and derives a magnitude of the anti-noise signal from both first and second signal; and an output to transmit the anti-noise signal to a speaker.

Abstract: A digital PLL may be combined with an analog PLL so that the output of the digital PLL is at a frequency high enough to maintain stability in the analog PLL when an initial reference clock signal is too low to maintain stability in the analog PLL. The digital PLL may include a scaling circuit, such as a frequency divider in the feedback path of the PLL, to generate the higher frequency output signal from the lower frequency reference input signal. The digital PLL may also use an on-chip free run ring oscillator as the clock for the digital PLL engine.

Abstract: In an aspect, in general, a programmable computation device performs computations of an inference task specified by a plurality of variables and a plurality of factors, each factor being associated with a subset of the variables. The device includes one or more processing elements. Each processing element includes a first storage for a definition of a factor, a second storage for data associated with the inputs and/or outputs of at least some of the computations, and one or more computation units coupled to the first storage and the second storage for performing a succession of parts of the at least some of the computations that are associated with a factor, the succession of parts defined by data in the storage for the definition of the factor.

Abstract: An approach to signal conversion adapts the signal conversion process, for example, by adapting or configuring signal conversion circuitry, according to inferred characteristics (e.g., probability distribution of value) of a signal being converted. As an example, an analog-to-digital converter (ADC) may be adapted so that its accuracy varies across the range of possible input signal values in such a way that on average the digital signal provides a higher accuracy than had the accuracy remained fixed. In another example, models (and corresponding inference circuitry) of both an input signal process and of a quantization process are used to improve signal conversion accuracy.

Abstract: A communication system for a power line is described. A transmission system of the communication system divides the time axis into a number of time slots synchronized such that one time slot can start about a zero crossing of the power line signal. These time slots are referred to as channels and are numbered from 1 to n. A modulation method is described to is narrow band continuous phase FSK, where a number m of modulating frequencies are used, arranged such that an integral number of full cycles fit into each channel time slot for all m frequencies. The system transmits during only a subset of the available time slots (channels) concentrated near the zero crossing of the power line waveform where the noise is typically minimal.

Abstract: A digital audio interface may include two signal inputs to transmit audio data. A first signal line may carry digital serial audio data. The second signal line may carry a word clock signal to differentiate the serial audio data transmitted over the first signal line. In the case of stereo audio data, the word clock signal may correspond to a left-right clock signal and may differentiate audio data intended for a right channel from that intended for a left channel. The audio data may also be differentiated differently depending on the configuration, such as in the case that the transmitted audio data include audio for more than two channels. The word clock signal may be scaled to regenerate a bit clock signal used to encode the serial audio data over the first signal line. The encoding bit clock signal need not be transmitted.

Abstract: Embodiments of the present invention may provide a power supply system that uses a capacitive voltage divider to selectively monitor various power supplies on an IC chip. The power supply system may sample a monitored power supply to a capacitor and select certain capacitors from a set of switched capacitors to divide down the sampled voltage. The resulting voltage may be compared to a voltage reference. Using different selections of switched capacitors, the monitored power supply may be compared for different voltage levels. The ratio of the sampling capacitor to the selected capacitors may determine a voltage level the comparator will trigger. Further, based on the monitored power supply level, the power supply system may turn on a switch between an external power supply and a regulated digital power supply to charge the regulated digital power supply while a main LDO is turned off.

Abstract: The present disclosure relates to an acupuncture meridian measurement system. The acupuncture meridian measurement system comprises: a signal generator configured to generate an alternating current excitation signal; an impedance measurer coupled to the signal generator and configured to measure a biological impedance between a fixed point to be measured and at least one selected point of an object; an acupuncture point determiner coupled to the impedance measurer and configured to locate an acupuncture point based on the measured biological impedance, wherein, the determined acupuncture point is a selected point, the biological impedance between which and the fixed point is less than a threshold. A technical problem solved by an embodiment of the present disclosure is to realize an accurate location of the acupuncture meridian. A use of an embodiment of the present disclosure is to locate acupuncture meridian and Yuan acupuncture points.

Abstract: A system for time-sequential LED-string excitation includes a controller coupled to at least two LED strings and arranged to sequentially excite the strings—preferably by pulse-width modulating their respective currents—such that each string conducts a desired current and/or provides a desired light intensity. Individual string currents and/or light intensities are provided to the controller as feedback signals. The controller preferably pulse-width modulates each string such that it conducts a current which approximates the performance that would be provided if the string were made to continuously conduct an ‘optimal’ current. A voltage converter may be included to provide the supply voltage connected to the top of each LED string, and to adjust the supply voltage as needed to ensure that each string conducts a desired current.

Abstract: A sink may be to used to process multimedia digital data. The sink may include a plurality of input ports, an output port, a switchably-enabled selector to select an input port from a plurality of HDMI input ports to couple to an output port, a control circuit to detect encrypted data in a channel of the input ports; and a plurality of decryption engines. Each of the decryption engines may be coupled to respective input ports to synchronize with a corresponding encryption engine of a data source after the control circuit detects encrypted data in the channel of the respective input port. Additional circuitry may be included to operate the sink in a power saving mode. Also, methods for processing the data in both power saving and non-power saving modes.

Abstract: An apparatus, system and method for controlling drive patterns is disclosed. A digital engine for controlling drive patterns may include a profile controller to program characteristics of one or more drive patterns for one or more piezoelectric actuators. The digital engine may further include a register array to store profile information for the one or more drive patterns. Each drive pattern may comprise a plurality of pulses with each pulse having a slope. The digital engine may also include a digital pattern generator to generate the one or more drive patterns based upon the profile information stored in the register array. The digital engine may further include a slope shaping circuit to modify one or more signals based upon an input from the digital pattern generator.

Abstract: A detection circuit is coupled to an output terminal of a driver circuit. The detection circuit includes a comparator to compare a signal at the output terminal to a reference signal corresponding to a signal that would be generated if a capacitive load having a relatively high capacitance value were connected to the output terminal. Output of the comparator is sampled at a predetermined time after the driver circuit provides the drive signal. An error signal is generated when the sampled output indicates that the capacitive load having the relatively high capacitance value is actually connected to the output terminal.

Abstract: A digital processor and method of operation utilize an alias address space to implement variable length instruction encoding on a legacy processor. The method includes storing instructions of a code sequence in memory; generating instruction addresses of the code sequence; automatically switching between a first operating mode and a second operating mode in response to a transition in instruction addresses between a first address space and a second address space, wherein addresses in the first and second address spaces access a common memory space; in the first operating mode, accessing instructions in the first address space; in the second operating mode, accessing instructions in the second address space; and executing the accessed instructions of the code sequence. Instructions of different instruction lengths may be utilized in the first and second operating modes.

Abstract: An uncalibrated converter element in an analog-digital converter may be replaced with two or more smaller elements having an effective total net value that is equal to that of the uncalibrated converter element. In an exemplary case where the element is capacitor, one or more of these smaller capacitors may be independently calibrated by switching the smaller capacitor between two voltages, such as a reference voltage and ground, and then calculating a difference of corresponding digital output codes generated by the backend ADC with previously calibrated capacitors associated with lesser significant bits. The total capacitance of the uncalibrated capacitor may be apportioned between the smaller capacitors so that the individual maximum charge contribution of each smaller capacitor to the converter output together with any expected manufacturing variance does not exceed the aggregated contribution of the previously calibrated capacitors.

Abstract: A resolution detector may be used in conjunction with an ADC to identify unresolved bits in a raw digital output of the ADC. Bits that have been properly resolved by the ADC may be distinguished from those that have not been successfully resolved, because of time limitations or other reasons. Each bit that has not been successfully resolved may be classified and referred to as an unresolved bit. If there are any unresolved bits detected in a sampling cycle, dither may then be incorporated in the raw digital output to compensate for the unresolved bits in that cycle. The dither may be added to the raw digital output of the ADC to eliminate any missing codes in the processed digital output codes or the dither may be substituted for the unresolved bits in raw digital output to generate the processed digital output.

Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.

Abstract: Metal oxide semiconductor (MOS) protection circuits and methods of forming the same are disclosed. In one embodiment, an integrated circuit includes a pad, a p-type MOS (PMOS) transistor, and first and second n-type MOS (NMOS) transistors. The first NMOS transistor includes a drain, a source and a gate electrically connected to the pad, a first supply voltage, and a drain of the PMOS transistor, respectively. The second NMOS transistor includes a gate, a drain, and a source electrically connected to a bias node, a second supply voltage, and a source of the PMOS transistor, respectively. The source of the second NMOS transistor is further electrically connected to a body of the PMOS transistor so as to prevent a current flowing from the drain of the PMOS transistor to the second supply voltage through the body of PMOS transistor when a transient signal event is received on the pad.

Abstract: The problem of inefficient channel impulse-response processing is addressed by processing different parts of a channel impulse response to accurately locate channel taps, and to generate more than one set of equalization coefficients. This allows the most-suited equalization coefficient to be selected based on a selection criterion.

Abstract: Apparatus and methods for demodulation are provided. In one embodiment, a method includes receiving an input signal having a frequency that varies in relation to a state of the signal, calculating a sine and cosine of a phase control signal, generating a first signal proportional to the sine of a product of a first quantity and the frequency of the input signal, generating a second signal proportional to the cosine of a product of the first quantity and the frequency of the input signal, and summing a product of the first signal and the cosine of the phase control signal with a product of the second signal and the sine of the phase control signal to generate a demodulator output for resolving the state of the input signal. In certain implementations, the phase control signal is controlled so as to reduce a frequency error of the input signal.

Abstract: Apparatus and methods for electronic amplification are provided. In one embodiment, a method includes providing a first differential amplification block, providing a second differential amplification block, electrically connecting the first and second differential amplification blocks in a stack between a first voltage reference and a second voltage reference, amplifying a first signal using the first differential amplification block, and amplifying a second signal using the second differential amplification block. A voltage difference between the first and second voltage references defines a power supply voltage, and the first differential amplification block operates over a first range of the power supply voltage and the second differential amplification block operates over a second range of the power supply voltage.