Abstract: A tunable impedance circuit can include a fixed impedance and one or more impedance selection circuits. Each impedance selection circuit can include a first impedance connected to a first interface terminal, a second impedance connected to a second interface terminal, and a plurality of series-connected transistors connected between the first and second impedances. Each impedance selection circuit can also include a plurality of drive impedance networks connected to gates, sources, drains, bodies, and isolation regions of the series-connected transistors, and a control circuit to provide a plurality of control signals to the drive impedance networks to turn on and turn off the series-connected transistors. For each impedance selection circuit, turning on and turning off the respective plurality of series-connected transistors can bring the series combination of the respective first and second impedances into and out of electrical communication with, e.g., into and out of parallel with, the fixed impedance.

Abstract: Circuits for generating a PTAT voltage as a base-emitter voltage difference between a pair of bipolar transistors. The circuits may form unit cells in a cascading voltage reference circuit that increases the PTAT voltage with each subsequent stage. The bipolar transistors are controlled using a biasing arrangement that includes an MOS transistor connected to a current mirror that provides the base current for the bipolar transistors. A voltage reference is formed by combining a PTAT voltage and a CTAT voltage at the last stage. The voltage reference may be obtained from the voltage at an emitter of one of the bipolar transistors in the last stage.

Abstract: Techniques to develop negative impedance circuits that may operate to their power supply rails. The techniques may include generating currents in response to voltage signals presented at respective input terminals of a negative impedance circuit. The voltage signals may be differential signals. The generated currents may be driven through a common impedance within the negative impedance circuit. The currents flowing through the common impedance may be mirrored back to the input terminals of the negative impedance circuit. The negative impedance circuit may be controlled to operate about a common-mode voltage for the circuit.

Abstract: Area-efficient voltage regulators are provided in which a first transistor has a first breakdown voltage and a first on-state resistance and a second transistor has a second breakdown voltage that exceeds the first breakdown voltage and a second on-state resistance that exceeds the first on-state resistance. With this arrangement, the second transistor can be biased to raise an output voltage. When the difference between an input voltage and the output voltage is less than a predetermined voltage, the second transistor is disabled and the first transistor is controlled to provide the output voltage at a wherein the controlling is preferably performed with a feedback control loop. The die area of the first transistor can be reduced because its on-state breakdown need only exceed the predetermined voltage rather than the substantially-higher input voltage.

Abstract: Apparatus and methods are disclosed, such as those involving a receiver device. One such apparatus includes an equalizer configured to process an input signal transmitted over a channel. The equalizer includes a first node configured to receive the input signal; a second node; and a programmable gain amplifier (PGA) having an adjustable gain. The PGA has an input electrically coupled to the first node, and an output electrically coupled to a third node. The equalizer also includes a high pass filter (HPF) having an input electrically coupled to the third node, and an output electrically coupled to the second node; and a control block configured to adjust one or more of the PGA or the HPF at least partly in response to a PGA output signal from the PGA or an HPF output signal from the HPF.

Abstract: An interface circuit for controlling a cross-domain signal link between a first circuit domain and a second circuit domain in a circuit may include first and second controllers, each of the first and second controllers including a first input coupled to a first voltage source of the first circuit domain and a second input coupled to a second voltage source of the second circuit domain.

Abstract: Bi-directional blocking voltage protection devices and methods of forming the same are disclosed. In one embodiment, a protection device includes an n-well and first and second p-wells disposed on opposite sides of the n-well. The first p-well includes a first P+ region and a first N+ region and the second p-well includes a second P+ region and second N+ region. The device further includes a third P+ region disposed along a boundary of the n-well and the first p-well and a fourth P+ region disposed along a boundary of the n-well and the second p-well. A first gate is disposed between the first N+ region and the third P+ region and a second gate is disposed between the second N+ region and the fourth P+ region. The device provides bi-directional blocking voltage protection during high energy stress events, including in applications operating at very low to medium swing voltages.

Abstract: Apparatus and methods are disclosed, such as those involving a receiver device. One such apparatus includes an equalizer configured to process an input signal transmitted over a channel. The equalizer can include a programmable gain amplifier (PGA) block which includes an input node configured to receive the input signal; an output node; and a programmable gain amplifier (PGA). The PGA amplifies the input signal with an adjustable gain. The PGA block also includes a gain control block having an input electrically coupled to the input node. The gain control block is configured to adjust the gain of the PGA at least partly in response to the input signal from the input node such that the PGA generates an output signal with a substantially constant amplitude envelope to the output node.

Abstract: A switch may include a MOS transistor alternatively operating in an ON phase and an OFF phase, a first voltage level shifter, and a second voltage level shifter. The MOS transistor may include a source for receiving an input signal, a drain for connecting to a load, and a gate. The first voltage level shifter may be selectively coupled between the source and the gate during the ON phase, and the second voltage level shifter may be selectively coupled between the gate and the source during the OFF phase.

Abstract: Disclosed is a micro-electro-mechanical switch, including a substrate having a gate connection, a source connection, a drain connection and a switch structure, coupled to the substrate. The switch structure includes a beam member, an anchor and a hinge. The beam member having a length sufficient to overhang both the gate connection and the drain connection. The anchor coupling the switch structure to the substrate, the anchor having a width. The hinge coupling the beam member to the anchor at a respective position along the anchor's length, the hinge to flex in response to a charge differential established between the gate and the beam member. The switch structure having gaps between the substrate and the anchor in regions proximate to the hinges.

Abstract: A switch circuit can include an impedance selection switch and a multi-output-resistance switch driver. The impedance selection switch can electrically connect an impedance to an input of an amplifier in response to a driver output signal, and include at least one transistor. The multi-output-impedance switch driver may provide the driver output signal to the switch, and have a first, relatively higher output resistance when providing a first logic state of the driver output signal to turn on the switch, and a second, relatively lower output resistance when providing a second logic state of the driver output signal to turn off the switch. The ratio of the first output resistance to the second output resistance can be greater than a selected predetermined ratio value.

Abstract: A method and apparatus for maintaining communication between an HDMI sources and an HDMI sink by monitoring data received from the HDMI source, and, based on the monitoring, dynamically switching between a first and a second mode without user intervention. The device may include a head end connector, a tail end connector and a cable. The head end connector may include a controller, a memory and an electrical signal transceiver. The controller may monitor data output from the source, and based on the outputted data; the controller may determine whether to maintain a first communication method or a second communication method.

Abstract: An analog-to-digital converter includes a plurality of sequentially cascaded stages, each stage including an amplifier and four copies of a circuit block including a flash and capacitors, in which the four copies of the circuit block operate interleavingly in a respective sample mode, pre-gain mode, gain mode, and reset mode of the circuit block, the copies of the circuit block in the sample mode, pre-gain mode, and reset mode are decoupled from the amplifier, and the copy of the circuit block in the gain mode is coupled to the amplifier to produce an output for a next following stage.

Abstract: Apparatuses and methods for electronic circuit protection are disclosed. In one embodiment, an apparatus comprises a well having an emitter and a collector region. The well has a doping of a first type, and the emitter and collector regions have a doping of a second type. The emitter region, well, and collector region are configured to operate as an emitter, base, and collector for a first transistor, respectively. The collector region is spaced away from the emitter region to define a spacing. A first spacer and a second spacer are positioned adjacent the well between the emitter and the collector. A conductive plate is positioned adjacent the well and between the first spacer and the second spacer, and a doping adjacent the first spacer, the second spacer, and the plate consists essentially of the first type.

Abstract: A pipeline stage of a pipelined analog-to-digital converter (ADC) circuit can include an ADC to convert an analog input to a digital output, a first plurality of digital-to-analog converters (DACs) sufficient in number to produce an analog output corresponding to the digital output, and a second plurality of DACs configured to have their output added into the analog output, where a succeeding pipeline portion can convert the amplified analog residue to at least one second digital output and a digitized residue. A mapping circuit can selectively exchange inputs between a selected one of the first plurality of DACs and one of the second plurality of DACs, and a calibration signal circuit can provide first and second calibration signals to inputs of the selected one of the first plurality of DACs and another of the second plurality of DACs.

Abstract: A switch can be implemented by a switch circuit, which can include a pair of NMOS transistors connected in series as pass-through transistors to transmit an input signal at an input terminal to produce an output signal at output terminal in response to an active state of a switching signal, and a pair of PMOS transistors connected in series as pass-through transistors to transmit the input signal at the input terminal to produce the output signal at output terminal in response to the active state of the switching signal. The switch circuit can also include a switch network connecting, in response to the active state of the switching signal, sources to bodies of the pairs of NMOS and PMOS transistors, and connecting, in response to an inactive state of the switching signal, the bodies of the pair of NMOS transistors to a first reference voltage, the bodies of the pair of PMOS transistors to a second reference voltage, and the sources of the pairs of NMOS and PMOS transistors to a third reference voltage.

Abstract: Disclosed is a micro-electro-mechanical switch, including a substrate having a gate connection, a source connection, a drain connection and a switch structure, coupled to the substrate. The switch structure includes a beam member, an anchor, an anchor beam interface and a hinge. The beam member having a length sufficient to overhang both the gate connection and the drain connection. The anchor coupling the switch structure to the substrate. The anchor beam interface coupling the anchor to the hinge. The hinge coupling the beam member to the anchor at a respective position along the anchor's length, the hinge to flex in response to a voltage differential established between the gate and the beam member. The switch structure having gaps between the substrate and the anchor in regions proximate to the hinges.

Abstract: Systems and methods to determine locations for dual touch operations performed on a four-wire resistive touch screen. The systems and methods may include measuring signals from pairs of electrodes on each of a first and second resistive sheet of the resistive touch screen in two phases of operation. The systems and methods may further include determining touch screen segment resistances from the signal measurements. The systems and methods may determine locations corresponding to the dual touch operations from the resistances. The systems and methods may also determine locations from the signal measurements.

Abstract: An integrated circuit fabricated with a number of layer may include a substrate, a transformer having a first winding, a second winding and a magnetic core. The first winding and the second winding may surround the magnetic core. The transformer may be disposed above a first side of the substrate. A flux conductor may be disposed on a second surface of the substrate opposite to the first surface.

Abstract: A method and a circuit for increasing a resolution of a digitally controlled oscillator include controlling the oscillator so that an output signal of the oscillator varies between semi-periods having a first frequency and semi-periods having a second frequency. The method and circuit further include applying the output signal of the oscillator as an input to a divider to obtain a divided signal. A frequency of at least one semi-period of the divided signal is a function of both an oscillator semi-period having the first frequency and an oscillator semi-period having the second frequency.