Abstract: A method for erasing an EEPROM cell which reduces the need for monitoring algorithms. The potential at the erase gate is initially raised and the potential at the control gate is lowered to cause FN tunneling through the erase gate. A subsequent soft programming step is employed to raise the potential at the control gate to a value sufficient to cause FN tunneling to start though the oxide of the transistor. A new memory device structure suitable for practicing this method employs a transistor having a floating gate, where a data value is stored as charged on the floating gate; a control gate; a control gate capacitor coupling the control gate to the floating gate; an erase gate; an erase gate capacitor coupling the erase gate to the floating gate; and an erase control circuit.

Abstract: A flow sensor has an inlet chamber with a first pressure sensor and an inlet port for receiving fluid, and an outlet chamber with a second pressure sensor and an outlet port. The flow sensor also has an anemometer in fluid communication with at least one of the two chambers.

Abstract: A power converter provides power across an isolation barrier, such as through the use of coils. A coil driver has transistors connected in a positive feedback configuration and is coupled to a supply voltage in a controlled manner by measuring the output power and opening or closing a switch as needed between the power supply and the coil driver. An output circuit, such as a FET driver, can be used with or without isolation to provide power and a logic signal.

Abstract: The present invention provides an improved technique for performing a near processing path exponent difference in an arithmetic logic unit (ALU) of a microprocessor. In one embodiment, an apparatus having a separate logic circuit for near processing path and far processing path subtraction generates exponent difference signals using only two least significant bits of exponents of the two floating point operands to perform the exponent difference.

Abstract: A gain matching method for a single bit gain ranging analog to digital converter including selecting, in response to a gain setting, a number of gain elements to be enabled in a multi-element gain controlled array interconnected between an analog input and an analog to digital converter, and patterning the enablement of the selected number of gain elements among the gain elements for matching the gain of the analog to digital converter for a range of gain settings of the converter to reduce in-band gain error due to gain element mismatch.

Abstract: A class G headphone amplifier circuit with improved power efficiency and low EMI. It may use an automatic signal level detector to detect the signal level of incoming signals and determine positive and negative power supplies for headphone amplifiers accordingly. A voltage generator may generate pairs of differential output voltages at a plurality of amplitude steps, and supply to headphone amplifiers the pair with the amplitude determined by the automatic signal level detector. As a result, headphone amplifiers are biased according to the input signal level, and the multiple voltage rails may improve power efficiency and avoid clipping.

Abstract: An analog to digital converter adapted to perform a first, more significant, part of a conversion as a successive approximation conversion, a pipeline conversion or a flash conversion and a second, least significant, part of a conversion as a sigma-delta conversion.

Abstract: A digital video interface receiver adjusts a transfer function of a phase-locked loop circuit having a programmable charge pump, a programmable phase-locked loop filter, or a programmable gain voltage controlled oscillator. The digital video interface receiver monitors and detects errors in a data stream associated with the phase-locked loop circuit. Moreover, the digital video interface receiver changes the transfer function of the phase-locked loop circuit, in response to the detected errors, by changing parameters associated with the programmable charge pump, the programmable phase-locked loop filter, or the programmable gain voltage controlled oscillator of the phase-locked loop circuit so as to change the transfer function of the phase-locked loop circuit.

Abstract: A signal conditioning circuit for a latching comparator comprising first and second transistors arranged in a long tail pair, the long tail pair having an active load and configured to act as an integrator.

Abstract: A digital signal processor receives samples of a first digital signal which is to be decimated and samples of a second digital signal which is to be interpolated. A digital signal processing engine performs a decimation function on samples of the first digital signal and an interpolation function on samples of the second digital signal on a time-shared basis. The digital signal processor has a first dual memory space for storing the samples of the first digital signal and a second dual memory space for storing the samples of the second digital signal. Outputs retrieved from a dual memory space are pre-added and applied to a multiplication and accumulation stage which operates on the pre-added outputs and a filter coefficient of a digital filter.

Abstract: A processing system includes a processing circuit having one or more buses, a memory interface unit to control access by the processing circuit to a memory, and a metrics module. The metrics module includes one or more metrics registers and a metrics controller to monitor one or more operations selected from memory interface unit operations and bus operations, and to store metrics information corresponding to the monitored operations in the metrics registers. The monitored operations can include memory access operations, arbitration operations, bus operations, and the like. The metrics information can be analyzed to provide a basis for improving performance of a program that is executed on the processing system.

Abstract: The invention is directed to a circuit and method for equalizing digital interference. A digital interference equalizing circuit may include a signal clipping unit, receiving a digital signal and clipping the digital signal based upon a clipping function, and a dithering unit adding dither to the clipped digital signal. A digital interference equalizing circuit may also include a noise detection circuit, detecting the normal activity level in a digital signal which may then be used to scale the dither added to the digital signal.

Abstract: A flexible engine for implementing digital signal processing (DSP) functions involving repeating various arithmetic/logical operations on a stream of data includes multiple programmable filter elements, at least one of which includes a microcode control program for internal control of the programmable filter element. The engine also includes programmable interconnection logic coupled to the programmable filter elements for selectively combining, scaling, and accumulating output values from the first plurality of programmable filter elements and selectively providing accumulated values as inputs to the first plurality of programmable filter elements. A filter controller coupled to the programmable filter elements and the programmable interconnection logic includes its own microcode control program for external control of the programmable filter elements and the programmable interconnection logic. Multiple engines can be combined to form larger, more powerful engines.

Abstract: A method and device for measuring active power of AC with respect to a fundamental frequency or harmonic frequencies using a DPLL include generating via the DPLL a pair of substantially mutually orthogonal sinusoid signals in response to an input voltage data signal, mixing a first sinusoid signal of the pair with a current data signal of the alternating current via a first low-pass filter, mixing the first sinusoid signal of the pair with a voltage signal of the alternating current via a second low-pass filter, and computing an active power of the alternating current based on a further mixing of an output from the first low-pass filter and an output from the second low-pass filter.

Abstract: A system and method for measuring reactive power which uses a pair of quadrate carriers to add a 90 degree phase shift to a voltage path or a current path in a power meter. The quadrate carriers have the same frequency but are offset in phase from each other by 90 degrees.

Abstract: The invention provides a sensor element formed in a first substrate and having a thermal barrier disposed between the sensor element and a heat source provided elsewhere on the first substrate. The thermal barrier includes at least one pair of trenches formed within the first substrate, individual trenches of the pair being separated by a cavity.

Abstract: The invention provides a method of processing a sequence of operands to produce compiled code for a target data processor, the method comprising the steps of: automatically analysing a source code to produce a fist representation of that code in single static assignment form; transforming the first representation into a second representation by unlooping ? nodes within the single static assignment form so as to create code suitable for tree pattern matching to be performed thereon; performing tree pattern matching on the second representation of the code; and re-looping the ? nodes.

Abstract: A technique for adding filler metal polygons in metal layers on a chip area of an IC design. In one example embodiment, this is accomplished by computing a size of a filler metal polygon using chip design layout data. One or more regions on the metal layers of the IC design that do not meet metal density requirements are then identified. The identified one or more regions are then filled with one or more filler metal polygons as a function of the metal density requirement and coupling capacitance between metal lines.

Abstract: A logic signal isolator comprising a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal, such that in response to a first type of edge in the logic signal, a signal of a first predetermined type is supplied to the primary winding and in response to a second type of edge in the logic signal, a signal of a second predetermined type is supplied to said primary winding, the primary winding and the transmitter being referenced to a first ground; and the secondary winding being referenced to a second ground which is galvanically isolated from the first ground and said secondary winding supplying to a receiver circuit signals received in correspondence to the signals provided to the primary winding, the receiver reconstructing the received logic signal from the received signals.

Abstract: A differential two-stage Miller compensated amplifier system with capacitive level shifting includes a first stage differential transconductance amplifier including first and second output nodes and an output common mode voltage, a second stage differential transconductance amplifier including non-inverting and inverting inputs and outputs and an input common mode voltage, and a level shifting capacitor circuit coupled between the first and second output nodes and the non-inverting and inverting inputs for level shifting between the output common mode voltage of the first stage and the input common mode voltage of the second stage.