Abstract: In one aspect, a resistor process invariant transconductor is provided. The transconductor comprises a voltage input configured to receive at least one voltage signal, a current output configured to provide at least one current signal, wherein a ratio between the at least one voltage signal and the least one current signal forms a total transconductance for the transconductor, and a circuit including at least one integrated resistor connected between the voltage input and the current output, the circuit adapted to maintain the total transconductance substantially constant across variation of the at least one integrated resistor.

Abstract: An integrated circuit includes a substrate, a storage device formed in the substrate to hold bias settings, and operational blocks formed in the substrate, each operational block including an operational circuit and a charge pump to provide well bias voltages to the operational circuit in response to one or more of the bias settings. A method for testing an integrated circuit having two or more operational blocks includes: (a) determining a maximum operating speed of each of the blocks at a minimum supply voltage; (b) selecting a block that has a slow operating speed; (c) selecting a well bias to speed up the selected block; (d) selecting a supply voltage to meet a target operating frequency at the selected well bias and measuring power; (e) repeating acts (b)-(d) while the measured power is less than a baseline power; and (f) saving the selected well bias and supply voltage settings for operation of the integrated circuit.

Abstract: A condensed Galois field computing system including a multiplier circuit for multiplying first and second polynomials with coefficients over a Galois field to obtain their product; and a Galois field linear transformer circuit for applying an irreducible polynomial of power n to the product including a partial result generator responsive to terms of power n and greater in the product for providing a folded partial result and a Galois field adder for condensing the folded partial result and the terms less than power n in the product to obtain Galois field transformer of power n of the product.

Abstract: A layered capacitor structure comprises two or more semiconductor/dielectric plates formed above an insulating surface which provides mechanical support, with the plates arranged in a vertical stack on the insulating surface. An insulating layer is on each plate, patterned and etched to provide an opening which allows the top of one plate to be in physical and electrical contact with the bottom of the subsequent plate. Contact openings are provided through the insulating layers, each of which provides access to a respective semiconductor layer and is insulated from any other semiconductor/dielectric plate. Electrical contacts through the contact openings provide electrical connections to respective semiconductor layers. The present structure can include as many stacked layers as needed to provide a desired total capacitance or range of capacitances.

Abstract: A ripple current reduction circuit includes a supply node coupled to the output of a high ripple voltage source such as a charge pump. A first current mirror is referred to the supply node and mirrors a current I1 to a second node, the mirrored current (I3) including a ripple current induced by the ripple voltage. A second current mirror is referred to the second node and mirrors a current I2 to an output node, which provides a current ILOAD to a load. The mirrors are sized such that the current provided at the second node is greater than the current required by the second mirror to provide ILOAD. The excess current, at least a portion of which includes a ripple component induced by the ripple voltage, is shunted to ground. As such, the magnitude of the ripple component in ILOAD is less than that present in I3.

Abstract: A harmonic detector including a pattern detector circuit responsive to a clock signal and a data signal configured to detect a target bit pattern from said data signal, and a time-out circuit responsive to said pattern detector circuit configured to detect the absence of said target bit pattern during a predetermined time-out parameter for indicating when said clock signal exceeds said data signal by a factor of two or more.

Abstract: Methods and apparatus are provided for controlling transmitted power in a wireless system. The method includes generating information to be transmitted as a series of signal bursts, with a time interval between successive signal bursts, controlling individually a power level of each of said signal bursts with a power control signal to provide output signal bursts to be transmitted, and asserting a new power value of the power control signal during the time interval preceding each signal burst. The wireless system can be a TDSCDMA wireless system, and the signal bursts can be uplink signal bursts.

Abstract: A programmable data encryption engine for performing the cipher function of an advanced encryption standard (AES) algorithm includes a parallel look-up table system responsive in a first mode to a first data block for implementing an AES selection function and executing the multiplicative inverse in GF?1(28) and applying an affine over GF(2) transformation to obtain a subbyte transformation and in a second mode to the subbyte transformation to transform the subbyte transformation to obtain a shift row transformation, and a Galois field multiplier for transforming the shift row transformation to obtain a mix column transformation and add a round key resulting in an advanced encryption standard cipher function of the first data block.

Abstract: A die has a part that is sealed with a cap. The seal can be hermetic or non-hermetic. If hermetic, a layer of glass or metal is formed in the surface of the die, and the cap has a layer of glass or metal at a peripheral area so that, when heated, the layers form a hermetic seal. A non-hermetic seal can be formed by bonding a cap with a patterned adhesive. The cap, which can be silicon or can be a metal paddle, is electrically coupled to a fixed voltage to shield the part of the die.

Abstract: A transistor cell includes a first stage comprising a first transistor that is coupled to a RC filter arrangement. A second stage has a second transistor that is coupled to the first stage. The linearity of the transistor cell is improved by shifting the DC bias point so that the first stage is biased at a high quiescent current while the second stage is biased at a low quiescent current.

Abstract: In one aspect, a method of transferring charge from a photosensitive array using a plurality of vertical shift registers each having a plurality of vertical elements including a first vertical element and a last vertical element, each of the plurality of vertical elements capable of storing charge, the plurality of vertical shifter registers, when operated, are capable of transferring charge from each of the plurality of vertical elements to a respective adjacent one of the plurality of vertical elements in a first direction from the first vertical element to the last vertical element, and using at least one horizontal shift register having a plurality of horizontal elements, each of the plurality of horizontal elements of the at least one horizontal shift register arranged to receive charge transferred from the last vertical element of a respective one of the plurality of vertical shift registers, the at least one horizontal shift register, when operated, capable of transferring charge from each of the plura

Abstract: One or more micromachined (MEMS) switches switch attenuators, such as resistors, into or out of a signal path, such as of a test instrument. The MEMS switches can be fabricated on the same substrate as the attenuators, or the switches or attenuators can be mounted on the same substrate as the others are fabricated. An instrument probe includes attenuators and MEMS switches that are controlled by the instrument and/or by a control circuit in the probe. Optionally, the probe includes reactive elements, such as capacitors, and MEMS switches to compensate for electrical characteristics of the probe and/or probe lead, and the probe or a test instrument automatically sets the MEMS switches to connect appropriate ones of the reactive elements to a signal path within the probe.

Abstract: A signal conditioning circuit dynamically adjusts a compression ratio, so as to compress a signal and avoid limiting to the extent possible, thereby avoiding distorting the signal by clipping. An input signal is applied to the input of a programmed gain amplifier (PGA) or other amplifier whose gain can be controlled by a gain control signal. The input or the output of the PGA is sampled by a level detector to produce a level signal that represents the level of the signal. A variable source produces a variable threshold signal. A comparator compares the level signal to the variable threshold signal to produce a difference signal. Control logic generates the gain control signal from the difference signal. When the level signal exceeds the threshold signal, the control logic alters the gain control signal to reduce the gain of the PGA, and when the level signal is less than the threshold signal, the control logic alters the gain control signal to increase the gain of the PGA.

Abstract: A compute system for executing an h.264 binary decode symbol instruction including a first compute unit having a range normalization circuit and an rLPS update circuit, and operating in a first mode responsive to current rLPS, range, value and current context to generate the next normalized range and next rLPS for the current context; a second compute unit including a value update circuit, a context update circuit, and value normalization circuit responsive to current rLPS, range value and current context to obtain the output bit, normalized value and the updated current context; and a third compute unit or said first compute unit operating in a second mode including a range circuit and a next context rLPS circuit responsive to rLPS range, value and next context to obtain a next context rLPS value.

Abstract: An apparatus and method is provided for optimizing LED driver efficiency. The present invention offers low cost solutions for powering LEDs while minimizing overall power dissipation in devices powered by a depletable power source. Low system cost is attained using a charge pump to increase LED drive voltage level and implementing combinations of drive techniques to overcome the inefficiency of the charge pump. A switch bypasses the charge pump when depletable power source output voltage is sufficient to directly drive an LED load. At certain output voltage levels, the switch can be opened causing the charge pump to boost drive voltage. The output voltage may also be PWM modulated to drive the LED load and, at some voltages, the depletable power source may drive the LED load directly. Efficiency levels of 90-97% are attainable.

Abstract: Equalization techniques in clock recovery receivers may include use of a passive equalizer prior to amplification, combined frequency paths in and active and/or passive equalizer, capacitive degeneration and/or negative feedback with low-pass filtering in an active equalizer, a decision feedback equalizer with multiple decision paths, and programmable tail currents to change switching points. A compensation circuit for a pre/post equalizer may include an oscillator fabricated from replica components to compensate for process variations and a look-up table to provide process variation correction in response to programmed equalizer settings.

Abstract: A high speed transmission system includes at least one transmitter; a buffer circuit for assembling into a data packet in parallel a number of sample conversion words from said transmitter; a marker circuit for adding a marker word to said data packet for framing said data packet; and a serializer circuit for serializing said data packet either before or after said marker word is added, with an embedded clock for transmission.

Abstract: A temperature setpoint circuit comprises bipolar transistors Q1 and Q2 which receive currents I1 and I2 at their respective collectors and are operated at unequal current densities, with a resistance R1 connected between their bases such that the difference in their base-emitter voltages (?Vbe) appears across R1. An additional PTAT current I3 is maintained in a constant ratio to I1 and I2 and provided to the collector of Q2 while Q2 is off, and is not provided while Q2 is on. The circuit is arranged such that Q2 is turned on and conducts a current equal to Ia when: ?Vbe=(kT/q)ln(NI1/Ia), where Ia=I2+I3, the temperature T at which ?Vbe=(kT/q)ln(NI1/Ia) being the circuit's setpoint temperature, such that the switching of current I3 provides hysteresis for the setpoint temperature which is approximately constant over temperature.

Abstract: A variable gain amplifier includes an attenuator having a plurality of pairs of tap points, and a plurality of pairs of gm cells, wherein each pair of gm cells is coupled to a corresponding pair of the tap points, and each pair of gm cells is constructed and arranged to operate as a multi-tanh cell.

Abstract: A method of forming a MEMS device provides a wafer having a base, a first conductive layer, a second conductive layer, and an intermediate conductive layer. After it provides the wafer, the method removes at least a portion of the intermediate conductive layer to form a cavity between the first and second conductive layers. At least a portion of the first conductive layer is movable relative to the base to form a diaphragm, while the second conductive layer is substantially immovable relative to the base. After it forms the cavity, the method seals the cavity.