Abstract: A DAC circuit is described which includes a DAC coupled to an amplifier. The circuit is configured to dynamically change the operating range of the amplifier depending on the circuit operating requirements. In this way the DAC circuit may be operable in one of a plurality of available ranges so as to have an extended range of operation.

Abstract: A DC to DC converter comprising an inductor, first and second electronically controllable switches and a controller, wherein the first electronically controlled switch is interposed between an input node and a first terminal of the inductor and the second electronically controllable switch extends between a second terminal of the inductor and the ground and where a first rectifier extends between the ground and the first terminal of the inductor and a second rectifier connects the second terminal of the inductor to an output node, wherein the controller controls the operation of the first and second switches to perform voltage step down or voltage step up, as appropriate, to achieve a desired output voltage; and wherein the controller is arranged such that the order in which the first and second switches are operated is maintained irrespective of whether the converter is stepping up the input voltage or stepping down the input voltage.

Abstract: An output stage, comprising a first transistor operable to pull a voltage at an output node towards a first voltage, and a rechargeable energy store having a potential difference between first and second terminals wherein the rechargeable energy store is arranged to be controllably connected between the output node and a second voltage supply such that the voltage at the output node can be driven to a voltage outside of a range defined between the first and second voltages.

Abstract: A method of forming a microphone forms a backplate, and a flexible diaphragm on at least a portion of a wet etch removable sacrificial layer. The method adds a wet etch resistant material, where a portion of the wet etch resistant material is positioned between the diaphragm and the backplate to support the diaphragm. Some of the wet etch resistant material is not positioned between the diaphragm and backplate. The method then removes the sacrificial material before removing any of the wet etch resistant material added during the prior noted act of adding. The wet etch resistant material then is removed substantially in its entirety after removing at least part of the sacrificial material.

Abstract: A voltage regulator system is disclosed for providing a regulated voltage supply. The voltage regulator system includes a power supply input node for receiving a power supply input voltage, a regulated voltage output node for providing a regulated output voltage, and a feedback circuit coupled to the regulated output voltage node and to a voltage regulator input node wherein a non-zero voltage is provided by the voltage regulator input node.

Abstract: A communication system includes a multi-channel signal regulation system that limits an aggregate signal in response to an indication that the aggregate signal exceeds a threshold value. The aggregate signal is formed from a combination of the input signals.

Abstract: An apparatus is provided for buffering instructions. An instruction store has memory locations for storing instructions. Each instruction can be associated with a timer such that an instruction dispatcher causes the instruction to be sent when the timer indicates that the instruction should be sent.

Abstract: A laser driver system is disclosed that includes a first monitor current output node, a power set node, and a first feedback path. The first monitor current output node provides a first monitor current output signal that is representative of one of a bias current and a modulation current of the laser driver system. The power set node receives a power ratio set signal that represents a desired relationship of a power required for the laser driver to produce a high power level threshold to a power required for the laser driver to produce a low power level threshold. The first feedback path extends from the first monitor current output node to the power set node, and may be used for adjusting the power set signal when the monitor current output signal becomes non-linear.

Abstract: A bandgap voltage reference circuit is described. By providing first and second bipolar devices that are operable with different current densities a base emitter voltage difference is created. This voltage difference is increased by coupling first and second cascode circuits to the first and second bipolars, the cascode circuits also being scaled relative to one another.

Abstract: A control system for a switching power supply shifts the phase of a PWM signal in response to a change in operating conditions. The phase may be shifted by resetting an oscillator that controls the PWM signal. Phase shift logic may include a sample-hold circuit that holds the value of an error signal when the PWM signal switches state. The held error signal may be compared to the real-time error signal, preferably with a user configurable offset. The output of the phase shift logic may be used to reset the oscillator.

Abstract: An improved ?? analog to digital converter system with automatic gain control response to out-of-band interferers including a ?? multibit analog to digital converter responsive to an analog input for providing a digital output including the in-band signal and out-of-band interferers and quantization noise and a signal peak estimator circuit responsive to the out-of-band interferers for generating a gain control signal for adjusting the gain of a variable gain element which may be an independent element such as a variable gain amplifier or it may be the analog to digital converter itself by virtue of its having an adjustable full-scale.

Abstract: A memory write timing system includes a modified memory bitcell including a storage device and a write/read circuit for writing/reading data to/from the storage device; and an output circuit for detecting the current state of the storage device.

Abstract: The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.

Abstract: The invention provides a thermal sensor having a first and second temperature sensing elements each being formed on a thermally isolated table in a first substrate.

Abstract: A repatterned integrated circuit chip package which balances and/or reduces the package capacitance associated with the gain resistor terminals to reduce the degradation of common mode rejection with frequency.

Abstract: A state machine circuit may be used to control a multiplexing circuit that selects and provides respective ones of multiple input clock signals to a clock-synthesizing circuit that generates a synthesized clock signal in response to such input clock signals. The state machine circuit may, for example, be configured so that the synthesized clock signal is a spread-spectrum clock signal and/or a clock signal having a nominal frequency that is greater than a nominal frequency of each of the input clock signals.

Abstract: Apparatus and method for performing a high-speed, low-power bit-wise comparison of two digital words. For each bit, a bit comparator is shown, employing a compare node and a discharge node. After both nodes are charged, the discharge node is discharged and the condition of the compare node signals the result of the comparison. For each bit, a bit comparator is provided including a single transistor switch across the compare node and the discharge node. An exclusive-OR circuit connected to receive the corresponding bits of the words drives and selectively actuates the switch when the values of the corresponding bits are mismatched. Words may be segmented such that comparisons may be done segment-wise and the detection of a mismatch in any segment obviates the discharging of the compare node in segments containing more significant bits, to save power.

Abstract: A circuit for synthesising a negative resistance, comprising first and second active devices, the first device having a control terminal connected to a first node, and the second device having a current flow terminal connected to the first node, and the first and second devices interacting with each other such that the circuit synthesises a negative resistance.

Abstract: A tuner having one or more digitally controllable tuning components may be coupled to an analog feedback compensation network in a target switching power supply controller to adjust the compensation while the power supply is operating. A communication interface couples the tuner to a host having a software interface to enable a user to adjust the values of the tuning components. The tuner may include components to adjust the values of a feedback network, an input network, a ramp adjust component, etc., on the target controller.

Abstract: A Successive Approximation Routine converter is provided in which a comparator is responsive to an output of a first Digital to Analog Converter, and an output of a second Digital to Analog Converter and to a DAC common mode output reference voltage, and wherein the comparator provides data to a SAR controller indicating which one of the DAC outputs is greater than the other, and how a common mode voltage on the DAC outputs compares to the reference voltage. On this basis the SAR controller can add or subtract a common mode offset to the trial words being presented at a given bit trial such that both differential and common mode convergence is achieved.