Abstract: An amplifier system includes an instrumentation amplifier arrangement being designed to amplify the difference between two voltage inputs with a defined gain, and to produce a single-ended output referenced to a known reference point. A front end circuit is coupled to the instrumentation amplifier. The front end circuit is configured to include a current clamp to actively limit the current in a gain resistor of the instrumentation amplifier to prevent input currents flowing when the instrumentation amplifier is over-driven.

Abstract: Aluminum or aluminum alloy on each of a pair of semiconductor wafers is thermocompression bonded. Aluminum-based seal rings or electrical interconnects between layers may be thus formed. On a MEMS device, the aluminum-based seal ring surrounds an area occupied by a movably attached microelectromechanical structure. According to a manufacturing method, wafers have an aluminum or aluminum alloy deposited thereon are etched to form an array of aluminum-based rings. The wafers are placed so as to bring the arrays of aluminum-based rings into alignment. Heat and compression bonds the rings. The wafers are singulated to separate out the individual semiconductor devices each with a bonded aluminum-based ring.

Abstract: A battery monitoring system is provided to monitor a battery stack having multiple cells connected in series. The monitoring system includes monitor modules to monitor respective subsets of the cells of the battery stack, each monitor module, in response to one or more control signals, measuring cell voltages of the respective subset of cells and providing at least one readout signal that represents the sampled cell voltages, the monitor modules being electrically connected in a stack such that each monitor module is referenced to the voltage of the respective subset of cells, and the control signals and the readout signal are connected through the monitor modules of the stack, and a system control unit to provide the control signals to the monitor modules and to receive the readout signals from the monitor modules.

Abstract: Converter systems are provided that use particular combinations of fixed and variable clock skewers to generate interleaved clock signals for the systems. These combinations have been found effective in accurately generating selectively-skewed clocks while simultaneously restricting the jitter that generally accompanies the skewing process.

Abstract: Circuits and methods for reducing distortion in an amplified signal are disclosed. The circuits and methods may use multiple single-ended gain stages to produce multiple amplified signals. The amplified signals may be processed in combination to produce a resulting output signal having little, or no, distortion. The circuits may be implemented on a single chip as integrated circuits.

Abstract: Virtual shielding is used to reduce the sources/origins of latchup and switching noise in a synchronous switching regulator. The regulator power stage may be split into two half stages. The ground bond wires of the half power stages may be positioned on opposite sides of the layout to substantially eliminate coupling between the ground bond wires. The power supply bond wire in one half power stage and the ground bond wire in the other half power stage may be positioned such that the mutual inductance between the power supply bond wire and the ground bond wire is maximized. The controller ground may be positioned substantially midway between the power supply bond wire in one half power stage and a respective ground bond wire in the other half power stage. The regulator controller may be placed between the regulator power stage and other analog circuitry to isolate the regulator power stage from the analog circuitry.

Abstract: A system and method of calibration develops a function from which is generated a monotonic time response; a gating period is defined from the monotonic time response and any error in the frequency of a reference signal is determined during the gating period; from that error an error signal is generated for adjusting the time constant of a circuit to be calibrated.

Abstract: An open drain driver (7) selectively switches a MOSFET switch (MN1) which is passively held in the conducting state into the non-conducting state. The MOSFET switch (MN1) switches an AC analogue input signal on a main input terminal (3) to a main output terminal (4) and the gate of the MOSFET switch (MN1) is AC coupled by a capacitor (C1) to the drain thereof. The open drain driver (7) comprises a first MOSFET (MN2) and a second MOSFET (MN3) through which the gate of the MOSFET switch (MN1) is pulled to ground (Vss). The gate of the first MOSFET (MN2) is coupled to the supply voltage (VDD) for maintaining the first MOSFET (MN2) in the open state. A control signal is applied to the gate of the second MOSFET (MN3) for selectively operating the open drain driver (7) in the conducting state for operating the MOSFET switch (MN1) in the non-conducting state.

Abstract: A method of producing a MEMS device removes the bottom side of a device wafer after its movable structure is formed. To that end, the method provides the device wafer, which has an initial bottom side. Next, the method forms the movable structure on the device wafer, and then removes substantially the entire initial bottom side of the device wafer. Removal of the entire initial bottom side effectively forms a final bottom side.

Abstract: A low noise voltage reference circuit is described. The reference circuit utilizes a bandgap reference component and may include at least one of a current shunt or filter to reduce high and low noise contributions to the output. Further modifications may include a curvature correction component.

Abstract: A controller for a multi-phase switching power supply shuffles the sequence of the phases in response to a load transient to prevent synchronization of one or more phases with high-frequency load transients. The sequence may be shuffled by varying the frequency and/or sequence of the switching control signals to introduce a random variation in the phases.

Abstract: An electronic chip has a data input for receiving an input digital data signal with a data frequency, a plurality of switches, and a logic circuit operatively coupled with both the plurality of switches and the data input. The logic circuit controls the switches to be in one of a DAC mode or a mixer mode. The DAC mode causes the switches to convert the input digital data signal into a DAC analog signal having about the data frequency. The mixer mode, however, causes the switches to convert the input digital data signal into a mixed analog signal having a mixer frequency that is higher than the data frequency.

Abstract: A DAC circuit is provided which implements a buffered DAC input where the buffer is provided by a differential amplifier whose supply rail is correlated with the input to the DAC. In this way it is possible to buffer the circuitry using amplifiers whose open loop gain specifications may be relaxed without affecting the linearity performance of the DAC.

Abstract: A low-noise programmable current source includes an output digital to analog converter for providing an output load current; and a control circuit, responsive to an input defining a predetermined load current for generating, for the digital to analog converter, a control word and a control voltage; the control word and the control voltage drive the digital to analog converter to produce the predetermined load current and the control voltage sets the compliance voltage of the digital to analog converter to minimize current noise in the digital to analog converter.

Abstract: A method for generating a digital signal pattern at M outputs involves retrieving an instruction from memory comprising a first set of bits identifying a first group of N outputs that includes fewer than all of the M outputs, and a second set of N bits each corresponding to a respective output included in the identified first group of N outputs. For each of the M outputs that is included in the identified first group of N outputs, the signal at the output is toggled if the one of the N bits corresponding to that output is in a first state and is kept in the same state if the one of the N bits corresponding to that output is in a second state. For each of the M outputs that is not included in the identified first group of N outputs, the signal at that output is kept in the same state.

Abstract: Multiplication engines and multiplication methods are provided for a digital processor.

Abstract: An apparatus for generating a digital signal pattern may comprises a memory, a program sequencer, first and second circuits, and an event execution unit. The memory may have stored therein a plurality of instructions that, when executed, cause a digital signal pattern to be generated on a plurality of nodes. The program sequencer may be configured to control a sequence in which the plurality of instructions are retrieved from the memory and executed. The first circuit may sequentially step through a plurality of different output states in response to a clock signal. The second circuit may identify an output event when an output state of the first circuit corresponds to an output state identified by retrieved instructions of a particular type. The event execution unit may control states of signals on the plurality of nodes in a manner specified by the retrieved instructions of the particular type in response to the second circuit identifying an output event.

Abstract: One disclosed circuit comprises a clock cycle counter circuit, a memory, and a clock cycle count comparison circuit. The clock cycle counter circuit may be configured to produce an output count. The memory may be configured to store at least first and second count values. The cycle count comparison circuit may be configured to compare the output count with each of the first and second stored count values and to generate a particular type of output event at a node if the output count corresponds to either of the first and second stored count values. Another disclosed circuit comprises a digital pattern generator, a general purpose output controller, at least one memory element, and a selection circuit. The digital pattern generator may be configured to generate a pattern of digital signals at M nodes. The general purpose output controller may be configured to generate general purpose digital signals at N nodes.

Abstract: A digital to analog converter (DAC) includes a first continuous-time stage that receives an input signal associated with a digital signal and performs continuous-time digital-to-analog conversion operations on the input signal. The first continuous-time stage outputs a first output signal. A second switched-capacitor stage receives the first output signal and performs switched-capacitor filtering of the first output signal. The second switched-capacitor stage outputs a second output signal that is sent to a low pass filter to form a continuous analog signal associated with the digital signal.

Abstract: An inertial sensor includes a cross-quad configuration of four interconnected sensor elements. Each sensor element has a frame and a resonator suspended within the frame. The sensor elements are arranged so that the frames of adjacent sensor elements are allowed to move in anti-phase to one another but are substantially prevented from moving in phase with one another. The sensor elements may be configured in a horizontally coupled arrangement, a vertically coupled arrangement, or a fully coupled arrangement. A pair of sensor elements may be vertically coupled.