Abstract: In one aspect, a calibration component configured to calibrate an automatic gain controller (AGC) for use in a tuner configured to isolate a selected channel from a multi-channel broadcast signal, the tuner implemented substantially on two chips, a first chip comprising a radio frequency (RF) integrated circuit adapted for RF processing and a second chip comprising a digital integrated circuit adapted for digital processing is provided.

Abstract: A method of forming a thick polysilicon layer for a MEMS inertial sensor includes forming a first amorphous polysilicon film on a substrate in an elevated temperature environment for a period of time such that a portion of the amorphous polysilicon film undergoes crystallization and grain growth at least near the substrate. The method also includes forming an oxide layer on the first amorphous polysilicon film, annealing the first amorphous polysilicon film in an environment of about 1100° C. or greater to produce a crystalline film, and removing the oxide layer. Lastly, the method includes forming a second amorphous polysilicon film on a surface of the crystalline polysilicon film in an elevated temperature environment for a period of time such that a portion of the second amorphous polysilicon film undergoes crystallization and grain growth at least near the surface of the crystalline polysilicon film.

Abstract: A voltage transformation circuit comprising a first input, a second input, a first output, first and second impedances and a current mirror having master and slave terminals, wherein the first impedance is connected between the first input and the master terminal of the current mirror, the second impedance is connected between the second input and the slave terminal of the current mirror, and the first output is connected to the slave terminal of the current mirror.

Abstract: A digital processor and method of operation utilize an alias address space to implement variable length instruction encoding on a legacy processor. The method includes storing instructions of a code sequence in memory; generating instruction addresses of the code sequence; automatically switching between a first operating mode and a second operating mode in response to a transition in instruction addresses between a first address space and a second address space, wherein addresses in the first and second address spaces access a common memory space; in the first operating mode, accessing instructions in the first address space; in the second operating mode, accessing instructions in the second address space; and executing the accessed instructions of the code sequence. Instructions of different instruction lengths may be utilized in the first and second operating modes.

Abstract: An integrated circuit for automatic calibration control of pin electronics is disclosed. The integrated circuit includes a substrate, and both pin electronics and a calibration circuit integral with the substrate. The calibration circuit is dedicated to a single channel of automatic testing equipment for a single pin of a device under test. Each sub-circuit of the pin electronics may include a replica output. The replica output is electrically coupled to the calibration circuit. The calibration circuit may include a multiplexor for receiving each of the replica outputs from the sub-circuits, such as a comparator, load and a driver, and for selectively switching between the replica outputs to determine calibration parameters for one or more levels of the sub-circuit. The calibration circuit includes a state machine capable of determining calibration parameters including offset and gain.

Abstract: A power converter provides power across an isolation barrier, such as through the use of coils. A coil driver has transistors connected in a positive feedback configuration and is coupled to a supply voltage in a controlled manner by measuring the output power and opening or closing a switch as needed between the power supply and the coil driver. An output circuit, such as a FET driver, can be used with or without isolation to provide power and a logic signal.

Abstract: In one aspect, a level shifter for shifting a voltage level from a first voltage level to a second voltage level and having a predictable power-up state is provided.

Abstract: A method of forming a microphone forms a backplate, and a flexible diaphragm on at least a portion of a wet etch removable sacrificial layer. The method adds a wet etch resistant material, where a portion of the wet etch resistant material is positioned between the diaphragm and the backplate to support the diaphragm. Some of the wet etch resistant material is not positioned between the diaphragm and backplate. The method then removes the sacrificial material before removing any of the wet etch resistant material added during the prior noted act of adding. The wet etch resistant material then is removed substantially in its entirety after removing at least part of the sacrificial material.

Abstract: A method of forming a MEMS device includes providing a first wafer having a MEMS structure in a first area and a second wafer having a second area, applying a metal nanoparticle material between the first wafer and the second wafer, and bonding a portion of the first wafer to a portion of the second wafer with the metal nanoparticle material so as to form a sealed area in the first area and the second area.

Abstract: A bandgap voltage reference circuit that can be implemented with low noise characteristics is described. To achieve such low noise, a bandgap reference circuit is provided that includes an amplifier coupled at its inputs to first and second transistors respectively, the transistors being arranged to generate a voltage representative of the base emitter voltage differences between each of the first and second transistors across a sensing resistor. The circuit additionally provides an additional current to the sensing resistor to reduce the noise contribution into the amplifier from the first transistor. Such a circuit may be corrected for second order temperature effects by inclusion of a temperature dependent current source.

Abstract: A bandgap voltage reference circuit that can be implemented with low noise characteristics is described. To achieve such low noise, a bandgap reference circuit is provided that includes an amplifier coupled at its inputs to first and second transistors respectively, the transistors being arranged to generate a voltage representative of the base emitter voltage differences between each of the first and second transistors across a sensing resistor. The circuit additionally provides an additional current to the sensing resistor to reduce the noise contribution into the amplifier from the first transistor. Such a circuit may be corrected for second order temperature effects by inclusion of a temperature dependent current source.

Abstract: In one aspect, a resistor process invariant transconductor is provided. The transconductor comprises a voltage input configured to receive at least one voltage signal, a current output configured to provide at least one current signal, wherein a ratio between the at least one voltage signal and the least one current signal forms a total transconductance for the transconductor, and a circuit including at least one integrated resistor connected between the voltage input and the current output, the circuit adapted to maintain the total transconductance substantially constant across variation of the at least one integrated resistor.

Abstract: An interface error monitor system for monitoring data exchanged between a controller and a data converter over an interface includes a multi-stage linear feedback shifter register associated with the data converter for generating a pseudo random number sequence; a signature generating circuit responsive to data exchanged between the controller and data converter for altering the pseudo random number sequence generated by the linear feedback shifter register to create a signature of the data.

Abstract: A drive arrangement for a micromachine includes a plurality of fixed electrodes arranged so as to have a common centroid.

Abstract: Methods and an apparatus are provided for interpolation of pixels in a pixel array having rows and columns of pixels. The apparatus includes a shift register array to shift pixel values of the pixel array, the shift register array including two or more shift registers; an interpolation filter array interconnected to the shift register array, the interpolation filter array including one or more interpolation filters; and a controller configured to provide pixel values in columns of the pixel array from the shift register array to respective interpolation filters in a first mode and configured to provide pixel values in rows of the pixel array from the shift register array to respective interpolation filters in a second mode. The controller may be configured to supply vertical sub-pixel values from the shift register array to the interpolation filters to generate diagonal sub-pixel values.

Abstract: In one embodiment, a circuit comprises at least first and second circuit stages, at least one level shifting circuit, and a control circuit. The first circuit stage is configured and arranged to produce a reference voltage at the at least one first output during each first phase of at least first and second phases, and to produce an output signal at the at least one first output that is responsive to an input signal at the at least one first input during each second phase of the at least first and second phases. The at least one level shifting circuit comprises at least one capacitor and at least one switch and is coupled between the first circuit stage and the second circuit stage.

Abstract: In one embodiment, a configurable timing generator outputs at least one timing signal. The configurable timing generator comprises a first timing generator configurable to output the at least one timing signal so that the at least one timing signal is adaptable to a plurality of applications. In one embodiment, a configurable parameter storage unit comprising a parameter storage area configurable so as to store a plurality of parameters at least partially defining a desired plurality of waveform hierarchy elements, where the desired plurality of waveform hierarchy elements enable the definition of a waveform. In one embodiment, a method of constructing a waveform for a configurable timing generator, the method comprising acts of constructing a first pattern waveform, where the first pattern waveform comprises a first basic pulse, and constructing a first sequence waveform, where the first sequence waveform comprises a plurality of repetitions of the first pattern waveform.

Abstract: In one embodiment, a configurable timing generator outputs at least one timing signal. The configurable timing generator comprises a first timing generator configurable to output the at least one timing signal so that the at least one timing signal is adaptable to a plurality of applications. In one embodiment, a configurable parameter storage unit comprising a parameter storage area configurable so as to store a plurality of parameters at least partially defining a desired plurality of waveform hierarchy elements, where the desired plurality of waveform hierarchy elements enable the definition of a waveform. In one embodiment, a method of constructing a waveform for a configurable timing generator, the method comprising acts of constructing a first pattern waveform, where the first pattern waveform comprises a first basic pulse, and constructing a first sequence waveform, where the first sequence waveform comprises a plurality of repetitions of the first pattern waveform.

Abstract: An input stage receives a differential input signal at first and second input nodes and provides a differential output current at first and second output nodes. The differential output current includes a component taken from the input nodes through first and second impedances, and an additional component generated in response to a sample of the voltage of the differential input signal. A transconductance cell having cross-coupled inputs may generate the additional component of the output current.

Abstract: A dual mode comparator circuit is disclosed. The dual mode comparator includes a plurality of differential transistor pairs. Each differential transistor pair includes a plurality of inputs and outputs. The outputs of the differential transistor pairs are coupled to inputs of a multiplexor. The multiplexor includes at least one control input for selecting between the multiplexor inputs and provides the selected input to the multiplexor output. The dual mode comparator further includes a comparator back end that is coupled to the output of the multiplexor. The comparator back end may include a folded cascode and additional gain stages. The comparator back end provides the comparator output to the next stage. The dual mode comparator may be used in automatic testing equipment embodiments.