Abstract: A gain-phase detector differentially processes the outputs from two logarithmic amplifiers to provide ratiometric gain measurement, thereby eliminating intercept as a parameter. Hard-limited outputs from the dual amplifiers are multiplied in a logarithmic scalable phase detector core to provide a calibrated phase measurement output. In the preferred embodiment, two logarithmic amplifiers and other circuitry are co-integrated on a single substrate to provide a high degree of matching between the amplifiers, thereby canceling errors in the individual frequency responses of the individual amplifiers, extending the usable frequency response, and improving effective noise figure. Other numbers of logarithmic amplifiers can be used, and their various outputs can be added, subtracted, multiplied and combined in other manners to produce continuous products, continuous quotients, mixtures of products and quotients, etc., all of RF demodulated signals.

Abstract: Converter systems are provided which complement sample capacitors in at least one converter stage with replica capacitors. The replica capacitors are switched to receive replica charges from the analog input signal during the same operational mode in which the sample capacitors receive undesirable remnant charges. In an initial portion of a subsequent operational mode, the remnant capacitors are briefly switched to the sample capacitors to substantially cancel the remnant charges. The sample capacitors then participate in obtaining input-signal samples during the remainder of the subsequent operational mode. Because the remnant charges have been substantially canceled, the accuracy of the subsequent operational mode is considerably enhanced. In another system embodiment, the replica capacitor is replaced by a discharge switch which provides a discharge path in an initial portion of the subsequent operational mode.

Abstract: Multiplication engines and multiplication methods are provided. A multiplication engine for a digital processor includes a first multiplier to generate unequally weighted partial products from input operands in a first multiplier mode; a second multiplier to generate equally weighted partial products from input operands in a second multiplier mode; a multiplexer to select the unequally weighted partial products in the first multiplier mode and to select the equally weighted partial products in the second multiplier mode; and a carry save adder array configured to combine the selected partial products in the first multiplier mode and in the second multiplier mode.

Abstract: A processing system includes a processing circuit having one or more buses, a memory interface unit to control access by the processing circuit to a memory, and a metrics module. The metrics module includes one or more metrics registers and a metrics controller to monitor one or more operations selected from memory interface unit operations and bus operations, and to store metrics information corresponding to the monitored operations in the metrics registers. The monitored operations can include memory access operations, arbitration operations, bus operations, and the like. The metrics information can be analyzed to provide a basis for improving performance of a program that is executed on the processing system.

Abstract: A DAC circuit is described which includes a DAC coupled to an amplifier. The circuit is configured to dynamically change the operating range of the amplifier depending on the circuit operating requirements.

Abstract: The present invention provides a JFET which receives an additional implant during fabrication, which extends its drain region towards its source region, and/or its source region towards its drain region. The implant reduces the magnitude of the e-field that would otherwise arise at the drain/channel (and/or source/channel) junction for a given drain and/or source voltage, thereby reducing the severity of the gate current and breakdown problems associated with the e-field. The JFET's gate layer is preferably sized to have a width which provides respective gaps between the gate layer's lateral boundaries and the drain and/or source regions for each implant, with each implant implanted in a respective gap.

Abstract: A method of testing a memory cell includes generating a logic low signal, generating a logic high signal, reducing the logic high signal to a level corresponding to the logic low signal plus an offset to produce a reduced logic high signal, providing the logic low signal and the reduced logic high signal to a memory cell, allowing the memory cell to achieve a memory state, and testing the memory cell to determine if the memory state is an expected memory state. A memory array has an array of memory blocks, a write select circuit to provide write data to the array of memory blocks, and a data retention test circuit to reduce write data having a level corresponding to a logic high to a level corresponding to a logic low plus an offset.

Abstract: A MEMS microphone has a backplate and a movable diaphragm that together form a variable capacitance. The backplate has a backplate surface and, in a corresponding manner, the diaphragm has a diaphragm surface that faces the backplate surface. At least one of the backplate surface and the diaphragm surface has at least a portion with a Hurst exponent that is less than or equal to about 0.5.

Abstract: A micromachined device has a body suspended over a substrate and movable in a plane relative to the substrate. The body has a perimeter portion, a first cross-piece portion extending from one part of the perimeter portion to another part of the perimeter portion to define at least first and second apertures, a first plurality of fingers extending along parallel axes from the perimeter portion into the first aperture, and a second plurality of fingers extending along parallel axes from the perimeter portion into the second aperture.

Abstract: An electronics package is described in which a quad flat no lead (QFN) electronic package has top and bottom surfaces. The bottom surface includes bottom contact pads arranged in a first pattern for electrical connection to corresponding package contact pads of an underlying circuit structure. The top surface includes top contact pads arranged in a second pattern for electrical connection to corresponding bottom contact pads of an overlying electronic package.

Abstract: An electronics package includes a wafer die substrate containing electronic circuits and having a top surface and a bottom surface. A top protective layer is substantially thinner than the substrate and covers the top surface. A bottom protective layer is substantially thinner than the substrate and covers the bottom surface. Circuit contacts are distributed about the bottom protective layer for electrically coupling the substrate electronic circuits to external electronic circuits.

Abstract: A method of addressing a target device within a chain of devices, the method comprising a sending device setting an address value and sending data in association with the address value, and wherein each device receiving the address value and data compares the address value to a device number, and if they are different modifies the address value by a predetermined amount and transmits the data and the modified address value to a subsequent device.

Abstract: A battery monitor for monitoring the performance of at least one battery within an array of batteries, comprising: a data acquisition device for measuring at least one parameter of the at least one battery associated with the battery monitor, a first data interface operable to exchange data with a first device, and a second data interface operable to exchange data with a second device.

Abstract: A method for obtaining virtual path identifier, virtual channel identifier, and encapsulation values in an asynchronous transfer mode access device for a network using either non-static or static internet protocol address assignments and asynchronous transfer mode adaptation layer 5. In the non-static environment, a plurality of discovery packets are generated, but in the static environment, a plurality of address resolution protocol packets are generated. Headers are added to the plurality of packets, such that a first set of packets, each packet including a logical link control header, and a second set of packets, each packet including a virtual channel multiplexed header, are realized. The first and second sets of packets are encapsulated and then transmitted to a central office.

Abstract: Methods and apparatus are provided for processing variable width instructions in a pipelined processor. The apparatus includes an instruction decoder configured to decode a loop setup instruction, having a loop setup instruction address, to obtain a loop bottom offset and configured to decode instructions following the loop setup instruction, each having an instruction address, to obtain an instruction width, registers for holding the loop setup instruction address and the loop bottom offset, and a loop bottom detector, responsive to a current instruction address, a current instruction width, the loop setup instruction address and the loop bottom offset, configured to determine if a next instruction is a loop bottom instruction.

Abstract: Control structures are provided to accurately maintain amplifier common-mode levels at the predetermined level of a common-mode reference voltage Vcm. The disclosed control structures provide amplifier feedback along a first feedback path that is configured to provide high gain and low bandwidth to closely maintain amplifier common-mode level at the predetermined level of a common-mode reference voltage Vcm. They also provide amplifier feedback along a second feedback path that is configured to provide wide bandwidth to substantially reduce perturbations of the common-mode level that would have otherwise been induced by input signal transients. In an important amplifier feature, these controls are obtained without use of structures (e.g., capacitors and switching transistors) that use substantial current which reduces amplifier efficiency.

Abstract: A microphone system has a base with at least one electrical port for electrically communicating with an external device. The system also has a solid metal lid coupled to the base to form an internal chamber, and a silicon microphone secured to the lid within the chamber. The lid has an aperture for receiving an audible signal, while the microphone is electrically connected to the electrical port of the base.

Abstract: A microphone has a movable diaphragm having a rest position, a stationary portion, and a set of springs movably coupling the diaphragm and the stationary portion. The diaphragm and stationary portion are spaced a first distance when the diaphragm is in the rest position. When not in the rest position, however, the diaphragm and stationary portion are capable of being spaced a second distance, which is greater than the first distance. Despite the change in distance, the diaphragm still is capable of returning the space from the second distance to the first distance when the diaphragm returns to the rest position.

Abstract: A multi-fferential amplifier system includes an amplifier having a plurality of amplifier inputs and a plurality of amplifier outputs; a plurality of input terminals for receiving a plurality of inputs and being interconnected with the amplifier inputs through a plurality of input impedances, respectively, and a feedback network including a plurality of summing circuits for combining the plurality of amplifier outputs in a plurality of different sets of groups each group numbering one fewer than the plurality, respectively, and feeding back the sum of each group of amplifier outputs to the remaining amplifier input for maintaining the difference between any group of amplifier outputs proportional to the difference of a corresponding group of inputs at the terminals and maintaining the average value of the amplifier outputs constant and unrelated to the inputs at the terminal.

Abstract: A capacitive sensor and a method of making it with a substrate having a diaphragm forming a first plate of a capacitor; a second fixed plate of the capacitor spaced from the diaphragm and defining a predetermined dielectric gap; a plurality of conductor elements interconnecting the substrate and fixed plate; and an edge lock supporting the fixed plate and the substrate relative to each other for maintaining the dimension of the defined gap independent of the conductor elements.