Abstract: An echo canceller includes an adaptive digital filter that generates an estimated echo signal {circumflex over (z)}[k] in response to (i) a sampled input data sequence x[k] and (ii) an error signal sequence e[k] indicative of the difference between a far end signal sequence y[k] and the estimated echo signal {circumflex over (z)}[k]. The adaptive filter includes N filter taps that each provide an associated tap output signal, wherein the adaptive digital filter generates the estimated echo signal {circumflex over (z)}[k] using the associated tap output signals from M of the N filter taps selected in response to a time delay estimate signal. The adaptive filter computes filter coefficients for each of the M number of the N filter taps using the associated tap output signals from the M number of said N filter taps.

Abstract: A dual mode transmitter for GSM and UMTS operation is provided. The GSM and UMTS paths share an oscillator and an intermediate frequency stage. Also, with the exception of the final stage of power amplification, the transmitter is provided as an integrated device.

Abstract: A current mirror includes an output stage that responds to a change in mirror output voltage with a change in output stage current, and an output compensation stage that, in response to the change in output stage current, introduces an output compensation current to oppose a change in mirror output current resulting from the change in output stage current.

Abstract: Bias networks are provided for accurate generation of biases of cascode transistor arrangements. Network embodiments generate a voltage that accurately biases the transistor of a cascode arrangement at a selected point in its saturation region and this voltage is accurately transferred to the drain of a transistor via the gate-to-source voltage drops of a pair of gate-coupled transistors.

Abstract: A method and apparatus for reducing unwanted harmonics in direct digital synthesizer (DDS) output. The method comprises the steps of providing a set of k phase-shifted clock signals, examining, in succession, each DDS accumulator state, and determining whether the DDS accumulator state has a defined transition-state. For each DDS accumulator state having a defined transition-state, an interpolation is performed based upon the value of the preceding DDS accumulator state, an element of the set of phase-shifted clock signals is selected based upon the interpolation, and the most significant bit (MSB) is repositioned using the selected element of the phase-shifted clock signals. The apparatus comprises means for providing a set of k phase-shifted clock signals, means for examining, in succession, each DDS accumulator state, and means for determining whether the DDS accumulator state has a defined transition-state.

Abstract: A reduced chop rate analog to digital converter technique including selectively weighting input samples to a digital filter, alternately inverting the polarity of an input error into positive and negative error components; and generating the positive and negative error components in a plurality of time response intervals of the digital filter in which the sum of the weights of the positive and negative error components are substantially equal.

Abstract: A high performance single-pole-double-throw (SPDT) Transmitter/Receiver (T/R) FET switch utilizes a plurality of multi-gate FETs in series to realize low insertion loss, low harmonic distortion and high power handling capabilities. The SPDT switch consists of an antenna port, a transmitter branch coupled to a transmitter port through a plurality of multi-gate FETs in series and a receiver branch coupled to a receiver port through a plurality of multi-gate FETs in series. When a high power signal passes from the transmitter port to the antenna port through the transmitter branch, the receiver branch is required to be shut off electrically to prevent the high power signal from leaking to receiver port. This leakage can degrade the isolation of the switch and cause harmonic distortion. Furthermore, the transmitter branch is required to provide a resistance as small as possible to reduce the power loss when it passes through the transmitter branch to the antenna port.

Abstract: A switching voltage converter, suitably a boost converter, employs an n-type transistor, preferably an NMOS FET, as a series switch, with its drain coupled to the cathode of the converter's diode and its source coupled to the converter's output node. A charge pump driven by the converter's switching voltage provides a voltage Von at the NMOS FET's gate input sufficient to turn the FET on. A series switch controller is arranged to, in response to a control signal, hold the NMOS FET off such that the converter's output voltage Vout is approximately zero regardless of the status of input voltage Vin, or allow the NMOS device to be turned on by Von.

Abstract: A voltmeter measures an unknown voltage on a target surface using multiple sampling stages or a parallel reference capacitor. A movable shutter may alternately be closed during resetting of a voltage measuring circuit and opened so as to expose a detector plate to the target surface during two sampling stages. Alternatively, the shutter may be used to modulate exposure of a detector plate to the target surface.

Abstract: A digital waveform synthesiser (1) is implemented as a single chip integrated circuit on a single chip (2) and comprises a direct digital synthesiser (10) which produces a synthesised output signal waveform on an output terminal (4) which is substantially phase and frequency locked to the phase and frequency of an externally generated input signal applied to an input terminal (5).

Abstract: A method for calibrating the sensitivity of a micromachined differential-capacitor accelerometer without applying mechanical stimulation, such as shaking. The accelerometer is fabricated with dimensional control structures so that a dimensional relationship is set-up among operational features of the device. The method includes measuring the resonant frequency of a movable mass and measuring the change in the output signal of the accelerometer as the mass is displaced by electrostatic means. The sensitivity of the accelerometer is then calculated.

Abstract: A hybrid tuning circuit is used consisting of a digital finite state machine and an analog tuning circuit to effectively keep the RC product of the continuous time integrator constant across process, temperature, supply, and sampling rate variations. Since the implementation is continuous, the tracking is more accurate than traditional techniques. Using a carefully chosen clocking scheme, the technique gets rid of inter-symbol interference in the feedback DAC. The technique does not use a reference frequency, thereby eliminating the need for a user to identify a reference frequency.

Abstract: A single wire bus communication system comprises a bus wire, a host device, and at least one client device, with each host and client device having pull-up and pull-down transistors to pull the bus wire “high” or “low”, respectively. The system is arranged such that, in response to a “trigger event” that requires responses from multiple client devices simultaneously, the host device enables its pull-down transistor, and each client device disables its pull-down transistor when conveying a “low” logic level onto the bus. To avoid bus contention, each client's pull-up transistor is arranged to conduct more current when enabled than the host's pull-down transistor. Then, one or more of the client devices' strong pull-ups will overcome the single weak pull-down on the bus, thereby enabling numerous client devices to respond to a command that requires a response from multiple clients.

Abstract: A DAC architecture is described. The architecture is specifically adapted to provided an analog voltage output based on a digital input word. The architecture includes a resistor ladder configuration sub-divisible into a first component, adapted to convert a lower part of the input word, and a second component adapted to convert an upper part of the input word. The DAC is calibrated such that the first component can be used to tune the output of the second component on selection of specific segment from the second component.

Abstract: Methods and apparatus for amplifying a tuner input signal are disclosed. One embodiment of the invention is directed to a tuner amplifier system comprising a tuner amplifier input that receives a tuner amplifier input signal and a first amplifier comprising an input and an output. The input of the first amplifier is coupled to the tuner amplifier input. The system further comprises a second amplifier comprising an input and an output, the input of the second amplifier being coupled to the tuner amplifier input, and a switch adapted to couple one of the first amplifier output and the second amplifier output to an output of the tuner amplifier. Another embodiment of the invention is directed to a method of amplifying a tuner input signal. The method comprises acts of detecting a power of the tuner input signal, selecting a tuner amplifier to amplify the tuner input signal based on the power of the tuner input signal, and amplifying the tuner input signal using the selected amplifier.

Abstract: An improved pipelined analog to digital converter that facilitates calibration for non-linearity errors and a method for obtaining calibration values. The analog to digital converter has a calibration mode in which the output bits for stages in the pipeline can be coupled to output pins of the device. Device pins that are used in normal operating mode to output the most significant bits of the ADC output are used in calibration mode to make available output bits of a pipeline stage being calibrated. A calibration method takes advantage of the outputs of the stages being directly observable to compute calibration values. The output bits of a pipeline stage are monitored as the analog input to the ADC is increased. A change in these bits identifies a subrange boundary. Errors are measured for values immediately above and immediately below each subrange boundary and used to compute correction factors.

Abstract: A SPDT switch includes an antenna port. A transmitter section is coupled to a transmitter port. The transmitter section includes a plurality of transistors that are coupled in series relative to each other. A receiver section is coupled to a receiver port. The receiver section includes a plurality of transistors that are coupled in series relative to each other, so that when the transmitter section transmits high power to the antenna port, the receive section is effectively off to provide isolation to the receive port. The receiver port is coupled to the receiver section using at least one external capacitor. The at least one external capacitor is used to improve the power handling capability and harmonic performance of the switch.

Abstract: A gain-phase detector differentially processes the outputs from two logarithmic amplifiers to provide ratiometric gain measurement, thereby eliminating intercept as a parameter. Hard-limited outputs from the dual amplifiers are multiplied in a logarithmic scalable phase detector core to provide a calibrated phase measurement output. In the preferred embodiment, two logarithmic amplifiers and other circuitry are co-integrated on a single substrate to provide a high degree of matching between the amplifiers, thereby canceling errors in the individual frequency responses of the individual amplifiers, extending the usable frequency response, and improving effective noise figure. Other numbers of logarithmic amplifiers can be used, and their various outputs can be added, subtracted, multiplied and combined in other manners to produce continuous products, continuous quotients, mixtures of products and quotients, etc., all of RF demodulated signals.

Abstract: A circuit and method are provided enabling the transfer of signals from a first voltage domain to a second voltage domain. The circuit comprises level shifters enabling the signal transfer, and is space-efficient and power efficient. A 3-wire serial protocol is used to enable the serial transmission of signals across the voltage domain boundary, and provides two distinct reset states.

Abstract: A method and device for self-test of a sensor. The method includes stimulating the sensor with signals that generate sensor outputs at a frequency that differs from the frequency of expected sensed parameter signals. The sensor output is filtered to remove the effects of the stimulation inputs, generating a sensed parameter signal. The unfiltered sensor output is compared to the expected output of the sensor with the stimulus input. A malfunctioning sensor may be detected by the comparison and appropriate action may then be taken.