Patents Assigned to Analog Devices
  • Frequency assisted digital timing recovery
    Patent number: 7050521
    Abstract: A method and system is provided for acquisition of the initial timing for a digital phase lock loop timing recovery system. A modified loop filter and post filter allows for an instantaneously change the oscillation frequency of a controllable oscillator and an instantaneous relative change of the sampling phase of the sampled data. These two features are used for initial timing recovery, in which the process of frequency and phase acquisition is separated into two independent steps. Once the initial timing is acquired, the timing recovery system is operated as a conventional digital phase lock loop timing recovery system to track additional frequency and phase drifts at the receiver with respect to the transmitter.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: May 23, 2006
    Assignee: Analog Devices, Inc.
    Inventor: Reza Alavi
  • Method and apparatus for autocalibrating a plurality of phase-delayed clock signal edges within a reference clock period
    Patent number: 7050919
    Abstract: A method for autocalibrating a plurality of phase-delayed clock signal edges within a reference clock period includes measuring delay spacing between the plurality of clock signal edges, calculating programmed delay spacing, calculating ideal signal edges from the programmed delay spacing and adjusting the clock signal edges to match the respective ideal signal edges. A plurality of calibrated clock signal edges is produced that are selectively available to a user.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: May 23, 2006
    Assignee: Analog Devices, Inc.
    Inventor: Kenneth Stern
  • Differential stage voltage offset trim circuitry
    Patent number: 7049889
    Abstract: Differential stage voltage offset trim circuitry involves the use of one or more trim circuits, each of which is dedicated to trimming one particular source of voltage offset (Vos) error for a “main” differential pair. One trim circuit may be dedicated to trimming Vos error that arises due to mismatch between the main pairs' threshold voltages, and another trim circuit may be dedicated to trimming Vos error that arises due to mismatch between the main pairs' beta values. Another trim circuit can trim Vos error due to gamma mismatch between the main pair transistors, and respective trim circuits can be employed to trim Vos error that arises due to threshold mismatch and/or beta mismatch between the transistors of an active load driven by the main pair. Several trim circuits may be employed simultaneously to reduce offset errors that arise from each of several sources.
    Type: Grant
    Filed: August 3, 2004
    Date of Patent: May 23, 2006
    Assignee: Analog Devices, Inc.
    Inventor: Arthur J. Kalb
  • Galois field polynomial multiplication
    Publication number: 20060106910
    Abstract: In one aspect, a multiplier for performing multiplication of a first operand and a second operand is provided. The multiplier comprises a matrix having a plurality of matrix elements arranged in a plurality of columns, a first plurality of storage elements to store at least a portion of the first operand, the first plurality of storage elements connected diagonally to the matrix, and a second plurality of storage elements to store at least a portion of the second operand, the second plurality of storage elements connected vertically to the matrix. In another aspect, a multiplier for computing at least a partial product of a first operand having a first length and a second operand having a second length is provided.
    Type: Application
    Filed: November 16, 2004
    Publication date: May 18, 2006
    Applicant: Analog Devices, Inc.
    Inventor: Wei An
  • DSP execution unit for efficient alternate modes for processing multiple data sizes
    Patent number: 7047271
    Abstract: In one embodiment, a digital signal processor (DSP) processes both n-bit data and (n/2)-bit data. The DSP includes multiple processing paths. A first processing path processes n-bit data. A second processing path is processes (n/2)-bit data. The multiple processing paths may be established using multiple components or may share components. When the processing paths share components, only one of the processing paths may be used at a time.
    Type: Grant
    Filed: April 20, 2004
    Date of Patent: May 16, 2006
    Assignees: Intel Corporation, Analog Devices, Inc.
    Inventors: Bradley C. Aldrich, Jose Fridman, Paul Meyer, Gang Liang
  • DAC having switchable current sources and resistor string
    Patent number: 7046182
    Abstract: A DAC architecture is provided which is monotonic in operation despite any mismatches in the components. The architecture is a segmented architecture and hence it is area efficient. This is achieved by effecting a generation of analog voltages by driving current sources to resistors in response to digital input. In a preferred embodiment, the invention provides a resistor string coupled between output and vref-, and set of current sources. The current sources are switched to nodes between resistors to generate voltages at the output.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: May 16, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Kaushal Kumar Ja, Arindam Raychaudhuri, Michael T. Tuthill, William Hunt, David A. Phelan, Colin G. Lyden
  • 2-1 Shuffling network
    Patent number: 7046181
    Abstract: A 2n?1 shuffling network includes a shuffle exchange network for receiving 2n?1 data inputs and a dummy input and providing 2n outputs; a replacement set of 2n?1 data switches for receiving 2n?1 outputs from the shuffle exchange network; and a selection circuit for actuating selective ones of the 2n?1 data switches in the replacement set to replace one of the 2n?1 outputs of the shuffle exchange network with a 2nth output of the shuffle exchange network.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: May 16, 2006
    Assignee: Analog Devices, Inc.
    Inventor: William G. J. Schofield
  • Semiconductor wafer comprising micro-machined components
    Patent number: 7045869
    Abstract: A semiconductor wafer having a matrix array of micro-mirrors comprises a component substrate carried on a base substrate. The component substrate comprises a membrane layer in which the micro-mirrors are formed and a supporting handle layer. The base substrate comprises a base layer from which a plurality of pedestals extend upwardly therefrom into cavities in the handle layer corresponding to the micro-mirrors. Each pedestal carries electrodes for co-operating with the micro-mirrors for tilting thereof. Conductors through vias in the pedestals connect the electrodes to electrically conductive tracks on a bottom surface, and in turn through conductors through vias to addressing terminals for addressing the electrodes.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: May 16, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Colin Stephen Gormley, Stephen Alan Brown, Scott Carlton Blackstone
  • Self-nesting interrupts
    Patent number: 7043582
    Abstract: A processor may support a self-nesting mode in which an interrupt may preempt another interrupt of the same priority level. The execution of an interrupt service routine (ISR) for an interrupt may be deferred until the ISR for a subsequently received interrupt of the same priority level is completed.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: May 9, 2006
    Assignees: Intel Corporation, Analog Devices, Inc.
    Inventors: Ravi P. Singh, Thomas Tomazin, Charles P. Roth, Jose Fridman, Michael Allen
  • Phase frequency detector with adjustable offset
    Patent number: 7042970
    Abstract: A phase detection apparatus is described for use in a phase lock loop (PLL). The apparatus has a first input for a reference signal, a second input for a loop feedback signal and an output for the phase difference signal. Two D-type flips flops are provided, the first being clocked with the reference signal and the second with the loop feedback signal. The output of the second flip-flop is delayed relative to the first flip-flop, thereby effecting minimal overlap, when using the phase detection apparatus in a fractional- N phase lock loop, of the interpolator activity with that of the charge pump.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: May 9, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Michael Keaveney, William Hunt, Michael Tuthill
  • Multi-surface mounting member and electronic device
    Patent number: 7040922
    Abstract: An electrical interconnect apparatus has a mounting member with a plurality of sides. The mounting member is formed from an insulator as a cuboid. Moreover, the mounting member also may be formed from a flexible circuit. Among other things, the plurality of sides includes an interface side. At least two of the plurality of sides are in electrical communication with the interface side.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: May 9, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Kieran P. Harney, Lawrence E. Felton, Lewis Long
  • Method for forming a micro-mechanical component in a semiconductor wafer, and a semiconductor wafer comprising a micro-mechanical component formed therein
    Patent number: 7041528
    Abstract: A method for producing a semiconductor wafer (1) with one or more micro-mirrors (5) formed in a membrane layer (2) which is supported on a handle layer (3) with a buried oxide layer (6) between the membrane and handle layers (2,3) which avoids rupturing of tethers (7) which support the micro-mirrors (5) in the membrane layer (2) and also avoids bowing of the micro-mirrors (5). After trenches (14) are formed in the membrane layer (2) for defining the micro-mirrors (5) and the tethers (7), and prior to forming of through bores (9) through the handle layer (3) to the micro-mirrors (5), a support layer (20) of oxide is deposited on the exposed surface (12) of the membrane layer (2) over the micro-mirrors (5) and the tethers (7) and is back filled into the trenches (14) for supporting bridging portions (16) of the buried oxide layer (6).
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: May 9, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Colin Stephen Gormley, Scott Jong Ho Limb
  • MOS varactor for LC VCOs
    Patent number: 7038527
    Abstract: A metal oxide semiconductor (MOS) varactor device has a source and a drain connected to each other, and a back gate, electrically separate from the source and drain, which is connected to a circuit common mode point.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: May 2, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Ward S. Titus, John G. Kenney, Jr.
  • Equalized SNR power back-off
    Patent number: 7039125
    Abstract: A power back-off system and method to mitigate far-end crosstalk interference between channels in a communication system through a generalization of the reference length and equalized FEXT methods, a power back-off method is provided that allows for control over the SNR of the channels by trading SNR on shorter channels against SNR on the longer channels. The generalization also provides for a power back-off method that can provide for two or more data rate service areas.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: May 2, 2006
    Assignee: Analog Devices, Inc.
    Inventor: Vladimir Friedman
  • Successive approximation analog-to-digital converter with pre-loaded SAR registers
    Patent number: 7038609
    Abstract: A SAR converter having enhanced performance by virtue of effectively pre-loading the SAR's most significant bits with a value that makes the associated DAC output almost equal to the signal to be converted. A normal SAR conversion is then completed with the SAR bits that have not been pre-loaded. The value used to pre-load the most significant bits of the SAR is preferably obtained from a low-resolution, high-speed converter, such as a flash. The range of DAC bits used in the normal SAR part of the conversion may be increased such that errors up to a certain magnitude in the high-speed converter can be corrected. Reducing power consumption of a SAR system can be readily accomplished by reducing comparator supply voltage. For a SAR converter architecture using a CAPDAC array or CAPDAC (capacitor array DAC), fairly large variations in comparator input voltage can be expected under these circumstances.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: May 2, 2006
    Assignee: Analog Devices, Inc.
    Inventor: Christopher Peter Hurrell
  • Voltage controlled oscillator having improved phase noise
    Patent number: 7038552
    Abstract: A frequency agile voltage controlled oscillator is provided in which amplitude control is performed by digitally controlling the current supplied to the oscillator from a current source (10). The use of digital control means that phase noise performance of the oscillator is not degraded by the introduction of noise from the current source controller.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: May 2, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Stephen Jonathan Brett, Jonathan Richard Strange, Paul Fowers, Christopher Geraint Jones
  • Integrated circuit bond pad structures and methods of making
    Patent number: 7038280
    Abstract: A bond pad structure for an integrated circuit includes first and second active devices formed in a substrate, first and second buses above the first and second active devices, respectively, a bond pad above the first and second buses, first interconnections between the first and second active devices and the bond pad, and second interconnections between the first and second active devices and the first and second buses, respectively. The first active device may be at least one PMOS transistor, and the second active device may be at least one NMOS transistor. A guard band region may be formed in the substrate.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: May 2, 2006
    Assignee: Analog Devices, Inc.
    Inventor: Alan W. Righter
  • Static dissipation treatments for optical package windows
    Patent number: 7033672
    Abstract: An optically transparent conductive material is used for static dissipation of a cover material for an optical switching device. The optically transparent conductive material is deposited directly or indirectly on the cover material. The optically transparent conductive material forms an electrically continuous film. The optically transparent conductive material can also be used for anti-reflection.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: April 25, 2006
    Assignee: Analog Devices, Inc.
    Inventors: John R. Martin, Maurice Karpman, Lawrence E. Felton
  • Valid bit generation and tracking in a pipelined processor
    Patent number: 7036000
    Abstract: In an embodiment, a pipelined digital signal processor (DSP) may generate a valid bit in an alignment stage. The valid bit may be qualified in a decode stage in response to receiving a stall signal and/or a kill signal. The valid bit output from the decode stage may be stored in a latch in an address calculation (AC) stage. The valid bit may be held in the latch by a latch enable circuit in response to receiving a stall signal. The valid bit output from the latch may be qualified in the AC stage. The circuit in the AC stage including the latch, the latch enable circuit, and a valid bit qualifier may be repeated in downstream pipeline stages, for example, the execution stages.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: April 25, 2006
    Assignees: Intel Corporation, Analog Devices, Inc.
    Inventors: Charles P. Roth, Ravi P. Singh, Gregory A. Overkamp, Thomas Tomazin
  • Digitally-realized signal generators and methods
    Patent number: 7034624
    Abstract: Signal generators are realized with combinations of a digital synthesizer (e.g., direct digital synthesizer), a frequency controller and a phase controller. The frequency controller receives a user-provided minimum count of a reference frequency wherein the minimum count is chosen to initially position a synthesizer signal within a selected frequency error of the reference frequency. In response, the frequency controller runs counters over a time sufficient to obtain the minimum count. The frequency controller then uses a difference count between the counts of the reference frequency and the synthesizer frequency to determine a controlled tuning word that properly positions the synthesizer signal. Subsequently, the phase controller detects phase differences between the reference signal and the synthesizer signal and applies phase correction signals to control the phase of the synthesizer signal.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: April 25, 2006
    Assignee: Analog Devices, Inc.
    Inventor: Ken Gentile