Abstract: An apparatus for compensating for variations in loop gain of a phase locked loop as a function of frequency, comprising a correction calculator for introducing a loop gain correction as a function of target frequency of a oscillator controlled by the phase locked loop.

Abstract: A system and method for suppressing RFI receives a differential input signal Vd, and a signal Vcm which varies with the common mode component of Vd. Vcm is phase-shifted and then amplified with a programmable gain G1 to produce an output VA1. A subtractor produces an output Vsub which varies with Vd?VA1. Vsub is amplified with a programmable gain G2 to produce an output VA2. An analog input signal processing circuit receives VA2 at an input which has an associated maximum dynamic range. A processor adjusts G2 such that VA2 covers the maximum dynamic range, adjusts the phase shift and G1 to minimize VA2, and adjusts G2 to increase VA2 such that it again covers the maximum dynamic range. The RFI in Vd is substantially subtracted out, thereby enabling the full dynamic range of the analog input signal processing circuit to be employed in receiving Vd.

Abstract: Simple, inexpensive waveform generators and methods are provided that generate curvilinear waveforms which comprise a fundamental sinusoid and harmonics that are either absent or are significantly reduced from the fundamental. In an exemplary method, a generator converts a first straight-line waveform into a level-shifted, frequency-doubled second straight-line waveform, multiplies the straight-line segments of the first and second waveforms to provide a first curvilinear waveform, and sums this curvilinear waveform with a scaled version of the first straight-line waveform to realize a second curvilinear waveform with further-reduced harmonics.

Abstract: A single chip digital frequency synthesiser (1) for synthesising a frequency swept synthesised output signal of a selectable frequency sweep comprises a direct digital synthesiser (5) which produces the frequency swept synthesised output signal on an output terminal (7) in response to values of a frequency control digital word applied to a frequency control input (8) thereof by an on-chip data processing circuit (25). An on-chip programmable data storing circuit (12) is programmable to store data indicative of a selected mode in which the digital frequency synthesiser (1) is to operate, and to store data indicative of selectable frequency and the time domains of the frequency swept synthesised output signal to be produced.

Abstract: A method for caching specified data in an n-way set associative memory with a copy-back update policy consists of the following steps. First, a row of the associative memory, organized as a plurality of rows and having n ways per row, is selected according to the main memory address of the specified data. The main memory provides primary storage for the data being cached. If one of the ways of the selected row holds invalid data, the specified data is cached in the way holding the invalid data and the data caching process is discontinued. If all n ways of the selected row hold valid data, the following steps are performed. First, a replacement strategy is used to select a way from the selected row. If the way selected in accordance with the replacement strategy holds unmodified data, the specified data is cached in the way selected by the replacement strategy and the data caching process is discontinued.

Abstract: In one particular embodiment, a processor receives and processes a plurality of instruction from a single instruction register. The processor loads the plurality of instructions into a single register and determines the number and size of instructions while the instructions are in the register. Each of the plurality of instructions is then simultaneously presented to the decoder. The decoder then decodes a first of the plurality of instructions and determines whether any additional instructions are present.

Abstract: An integrated digital calibration circuit and digital to analog converter includes a digital to analog converter (DAC) and a digital calibration circuit including a memory for storing predetermined end point coefficients of the digital to analog converter transfer function; and an arithmetic logic unit for applying the end point coefficients to the DAC input signal to adjust the end points of the DAC and/or analog signal chain.

Abstract: In one embodiment, a programmable processor is adapted to support hardware loops. The processor may include hardware such as a first set of registers, a second set of registers, a first pipeline, and a second pipeline. Furthermore, the processor may include a control unit adapted to efficiently implement the hardware when performing a hardware loop.

Abstract: The invention relates to integrated circuit package devices including at least two component chips. In particular the invention describes such devices having a transformer provided between the two components chips, the transformer providing isolation between the component chips and wherein the total assembly is sufficiently small that it can be integrated in standard IC packages.

Abstract: A method for computing an out of place FFT in which each stage of the FFT has an identical signal flow geometry. In each stage of the presently disclosed FFT method the group loop has been eliminated, the twiddle factor data is stored in bit-reversed manner, and the output data values are stored with a unity stride.

Abstract: An impedance network configuration in the form of a snake-like or ladder structure is provided. The ladder configuration enables the provision of tabs extending outwardly from the normal conducting path, the tabs providing a location for the provision of contact layers. Using such a configuration the contribution of the contact impedance can be minimized and also programming of the configuration may be effected.

Abstract: A radio transceiver suitable for use in a mobile telephone is provided. The transceiver is operable in dual modes so as to be able to operate with both GSM and UMTS systems. In a preferred embodiment the transmitter section receives base band signals and up-converts them to an intermediate frequency of approximately 450 MHz. This is then mixed with local oscillator frequency of approximately 1.35 GHz, such that a difference frequency allows operation in the GSM 850/950 MHz band, and the sum frequency allows operation in the GSM 1800/1900 MHz bands. The frequency addition allows operation in the UMTS band. The receiver portion of the transceiver comprises a direct conversion receiver for down-converting the received signal without use of an intermediate frequency.

Abstract: A method for use in a wireless communication system includes performing at least part of physical layer processing in one or more digital signal processors of a selected type, and performing at least part of medium access control processing in the same one or more digital signal processors. The physical layer processing may include coding, spreading and modulation. The medium access control layer processing may include placing data units in queues according to priority and scheduling data units for transmission or retransmission.

Abstract: A movable microstructure includes a first finger set comprising two or more first fingers affixed to a substrate and extending substantially parallel to a defined displacement axis towards a proof-mass. The movable microstructure further includes a second finger set comprising at least one second finger, each member of the second finger set extending substantially parallel to the displacement axis from the proof-mass, terminating between two first fingers. Each second finger is substantially closer to one of the two first fingers between which it terminates. The first finger set, in conjunction with the second finger set, form two terminals of a capacitor. An electrical circuit is included that provides a voltage across the capacitor to generate a position-dependent force, the position-dependent force having a component along an axis substantially orthogonal to the displacement axis, the magnitude of the position-dependent force varying in proportion to displacement along the displacement axis.

Abstract: Methods and controllers are provided to estimate and reduce phase errors between converters of time-interleaved analog-to-digital systems by generating corresponding error signals in the form of difference signals. The difference signals concern differences between magnitudes of first adjacent samples and interleaved second adjacent samples of the converters. The difference signals can be applied (e.g., to a converter's input sampler or to a variable delay element inserted after the converter) to substantially reduce the phase errors. The methods and controllers may be economically implemented because they can be realized with simple operations (e.g., addition and subtraction). Although some embodiments are facilitated with knowledge of parameters of the analog input signal, others do not require this knowledge so long as the signal is restricted to lie within a single Nyquist zone.

Abstract: An apparatus for controlling the state variable of an integrator stage in a modulator including a detector circuit for generating an overload signal when the modulator is overdriven, a control circuit responsive to the overload signal for generating switching control signals during the overdriven condition, and an integrating capacitance circuit having an unswitched portion and a switched portion and responsive to the switching signals for repeatedly connecting the switched portion between the unswitched portion and a discharge path to receive and drain charge when the modulator is overdriven to increase the lossiness of the integrator stage and control a state variable of the modulator.

Abstract: A single-wire digital interface for receiving digital data as a stream of pulses, with ‘1’ and ‘0’ logic levels represented with pulses having “first” and “second” pulse widths, respectively. A low-pass filter produces an output that increases at a known rate for the duration of a received data pulse, and a comparator produces an output that toggles when the filter output exceeds a predetermined threshold. A clock edge is generated when a received pulse terminates; the clock and comparator outputs are provided to a latch circuit. The interface latches a ‘1’ when the received pulse's width is equal to the “first” pulse width, and latches a ‘0’ when the received pulse's width is equal to the “second” pulse width. Data is preferably preceded by a “start-of-packet” (SOP) bit pattern and followed with a “end-of-packet” (EOP) bit pattern.

Abstract: A new output mask for a m-sequence generator is produced by modulo-2 summing a number of intermediate masks. The intermediate masks are produced by shifting a shift template by amounts corresponding to offsets of set bits in an existing output mask. If an intermediate mask contains set bits beyond its portion corresponding to the new output mask, then they are wrapped back.

Abstract: Apparatus for determining a value, a sign and an overflow status of an addition of at least three n-bit data inputs. The apparatus comprising: a first adder, for adding the at least three n-bit data inputs, to provide a first output having at least 2n bits; a second adder for adding a portion of bits of the first output, the second adder being operable to add a plurality of m-bit addends, m being smaller than or equal to n. The apparatus further comprising at least two electronic-circuits, operatively associated with the first adder and the second adder. The first adder, the second adder and the at least two electronic-circuits are constructed and designed to obtain the value, the overflow status and a sign of the addition of the at least three data inputs, using predetermined parity rules being associated with a parity characteristic of the at least three data inputs.

Abstract: This disclosure describes a method for operating a cooling device in a thermal system that is responsive to an operating parameter and dynamically changes the operating parameter to achieve a maximum operating temperature for any system regardless of the subsystem variation.