Abstract: An apparatus has first and second wafers, and a conductive rim between the first and second wafers. The conductive rim electrically and mechanically connects the first and second wafers. In addition, the conductive rim and second wafer at least in part seal an area on the surface of the first wafer.

Abstract: Differential processing systems are provided that reduce even-order harmonic energy. The reduction may be selectively converted to, for example, random noise. This effects a tradeoff for processing systems that can afford to accept some increase in noise to thereby gain the benefits of reduction in even-order harmonic energy. In one system embodiment, first and second signal portions of a differential signal are respectively processed along first and second signal paths in a first processing mode and along the second and first signal paths in a second processing mode. The modes are selected to perform the desired conversion of even-order harmonic energy. In another system embodiment, first and second signal portions of a differential signal are processed along first and second signal paths in a first processing mode and inverted versions of these signals are processed along the first and second signal paths in a second processing mode. In addition, output signals are inverted in the second processing mode.

Abstract: Quadrature suppression is provided by placing a resonator mass adjacent to a quadrature suppression electrode. The resonator mass is capable of moving substantially parallel to the quadrature suppression electrode and includes a notch formed adjacent to a portion of the quadrature suppression electrode such that a length of resonator mass that is directly adjacent to the quadrature suppression electrode varies as the resonator mass moves relative to the quadrature suppression electrode. The quadrature suppression electrode is capable of producing a lateral force on the resonator mass that varies based on the length of resonator mass that is directly adjacent to the quadrature suppression electrode. Such quadrature suppression can be used in sensors having one or more resonator masses.

Abstract: The invention relates to a cascaded scheme in which an RRC filter, a modified RRC filter or other digital filter is implemented at a relatively low data rate, such as twice the symbol or chip rate, or 2×. Interpolation filters are used to increase the data rate to a higher data rate, such as 8×. Decimation filters are used to reduce the data rate from a higher rate, such as 8×, to a lower rate, such as 2×. The coefficients of the digital filter may be adjusted to compensate for characteristics of other components across the entire filter chain. Most of the implementation complexity of the filter chain is consolidated into the relatively low rate (such as 2×) digital filter while interpolation or decimation filters can be implemented at very low cost. The compensation capability provided by the digital filter makes design of simple decimation or interpolation filters much easier.

Abstract: A first device receives and processes signals from a communication link that supports a plurality of signal protocols. The device comprises a converter, coupled to the communication link, that outputs a sampled data stream, and a digital filter that filters the sampled data stream to separate signals associated with different signal protocols. A second device receives a first input sampled data stream representative of a first signal to be transmitted and associated with a first signal protocol and a second input sampled data stream representative of a second signal to be transmitted and associated with a second signal protocol, and combines the data streams into an output data stream which may be coupled to the communication link.

Abstract: A programmable fuse state determination system and method provide a fuse current through a programmed fuse which produces a voltage that varies with the fuse's resistance. The voltage is compared with a threshold voltage to indicate whether the fuse is blown or intact. The invention employs ‘normal’ and ‘test’ modes, in which the relationship between the fuse's resistance and the threshold voltage differ, such that a higher fuse resistance is required for the fuse to be determined blown in the ‘test’ mode than in the ‘normal’ mode.

Abstract: An image processor that calculates values that are related to distortion between two image parts. The values are detected in a previous calculation. Those values are then used in the next calculation cycle to detect an early exit. That value, called least, divided by the number of accumulators, and its negative is loaded into the accumulators. When the accumulators reach zero, an early exit is established.

Abstract: A programmable processor that includes a pipeline with a number of stages. A stall controller is associated with the pipeline, and detects a hazard condition in at least one of those stages. The stall controller produces a set of signals that can control the stages individually, to stall stages of the pipeline in order to avoid a hazard. In an embodiment, a bubble is formed in the pipeline which allows one instruction to complete prior to allowing the pipeline to continue.

Abstract: Synthesizers are provided to generate synthesizer signals in response to primary digital signal representations that are created by a signal generator. In an important feature, the synthesizers further include a signal corrector that inserts correction digital signal representations to at least partially cancel a corresponding spurious component in the primary digital signal representation and thereby provide synthesizer signals with reduced spurious content.

Abstract: Methods and structures are provided that reduce conversion errors in pipelined analog-to-digital converters which are induced in one converter cycle by component memory of signals in one or more preceding converter cycles. The methods and structures include the use of digital filters that provide a digital representation of the residue of a preceding converter cycle, multiply this representation by an appropriate memory parameter, and sum the product with the digital representation of the residue of a current converter cycle to thereby reduce the memory effect. The methods and structures also form capacitors of switched-capacitor converter structures with sub-capacitors that are reconfigured (e.g., reversed or alternated between differential sides of differential amplifiers) in different converter cycles.

Abstract: A switched-capacitor circuit for use in analog-to-digital conversion samples an input signal with respect to a reference voltage such that it significantly reduces a DAC settling time interval during each bit trial. In one exemplary embodiment, the switched-capacitor circuit having first and second groups of capacitor banks is coupled to a first input of a comparator and to a control circuit which provides control signals such that during a switching sequence, an equal value of capacitance is selected from each of the first and second groups of capacitor banks to reduce the DAC settling time interval, thereby improving the conversion rate.

Abstract: A wafer cap protects micro electromechanical system (“MEMS”) structures during a dicing of a MEMS wafer to produce individual MEMS dies. A MEMS wafer is prepared having a plurality of MEMS structure sites thereon. Upon the MEMS wafer, the wafer cap is mounted to produce a laminated MEMS wafer. The wafer cap is recessed in areas corresponding to locations of the MEMS structure sites on the MEMS wafer. The capped MEMS wafer can be diced into a plurality of MEMS dies without causing damage to or contaminating the MEMS die.

Abstract: Cascode bias structures are provided which enhance control of cascode biases over disturbing effects such as temperature and process variations. Because this enhanced control stabilizes the biases over these disturbing effects, the biases can be reduced to thereby expand the cascode's dynamic range and yet assure that the cascode transistors continue to operate in their proper transistor regions.

Abstract: A digital latch includes a latch circuit having first and second data inputs, first and second data outputs, and a clock signal input. The latch circuit has a first load value relative to a clock driver when data at the first and second data inputs is non-changing. The latch circuit has a second load value relative to a clock driver when data at the first and second data inputs is changing. The digital latch further includes a load compensation circuit operatively connected to the first and second data inputs of the latch circuit and to the first and second data outputs of the latch circuit.

Abstract: A beam steering module comprised of a mirror stack array in close proximity to a collimator array controllably steers photons along two axis and in a direction substantially less than 90 degrees to the collimator orientation. Several configurations of the module are described using single and double axis mirror rotation and relay optics. Optical telecommunications switches are shown using modules coupled to each other along flat and curved surfaces, with and without use of fold mirror and enabling a plurality of configuration options including photodetector optical power monitoring schemes that require no external power taps.

Abstract: A new partial product bit generator is used to generate a partial product bit PPji. In some embodiments, the partial product bit generator generates the partial product bit PPji from intermediate signals that are able to be generated concurrently, for example in two levels of combinatorial logic. The partial product bit PPji is then able to be generated from the intermediate signal, for example in only one level of combinatorial logic. In such embodiments, a long series of combinatorial logic operations is not required.

Abstract: An inertial sensor has an interior filled with a relatively low viscosity fill gas. To that end, the inertial sensor has a housing forming the noted interior, and a movable component within the interior. The inertial sensor also has the noted fill gas within the interior. The fill gas has a viscosity that is less than the viscosity of nitrogen under like conditions. For example, when subjected to the same temperatures and pressures, the fill gas has a viscosity that is less than the viscosity of nitrogen.

Abstract: A DAC architecture is described. The architecture is specifically adapted to provided an analog voltage output based on a digital input word. The architecture includes a resistor ladder configuration sub-divisible into a first component, adapted to convert a lower part of the input word, and a second component adapted to convert an upper part of the input word. The DAC is calibrated such that the first component can be used to tune the output of the second component on selection of specific segment from the second component.

Abstract: A sub-ranging DAC converter is provided where voltage followers rather than operational amplifiers are used to avoid loading a main resistor string.

Abstract: A JFET switch select circuit including a first current mirror system including a first high current mirror circuit referenced to high rail voltage and a first low current mirror circuit referenced to a low rail voltage, a second current mirror system including a second high current mirror circuit referenced to the high rail voltage and a second low current mirror circuit referenced to the low rail voltage, and a comparator circuit responsive to an input voltage and a reference voltage for directing current from a current supply circuit to one of the first and second high current mirror circuits and one of the first and second low current mirror circuits for saturating a switching device of one of the first and second high current mirror circuits to set a first output voltage proximate to a high rail voltage and for saturating a switching device of one of the first and second low current mirror circuits to set a second output voltage proximate a low rail voltage.