Patents Assigned to Analog Devices
  • Patent number: 6732235
    Abstract: A digital signal processing system includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masters each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.
    Type: Grant
    Filed: November 6, 2000
    Date of Patent: May 4, 2004
    Assignee: Analog Devices, Inc.
    Inventors: Paul D. Krivacek, Jørn Sørensen, Frederic Boutaud
  • Publication number: 20040080373
    Abstract: A programmable frequency synthesizer including a voltage-controlled oscillator, a regenerative frequency divider and a programmable integer divider, that provides wideband frequency coverage from a single narrowband oscillator. The voltage-controlled oscillator may generate a first signal having a first frequency. The regenerative frequency divider is coupled to the voltage-controlled oscillator and receives the first signal and performs a fractional multiplication of the first frequency of the first signal to provide a second signal a having a second frequency. The programmable integer divider is coupled to the regenerative frequency divider, and receives the second signal and divides the second frequency by a predetermined integer to provide a third signal having a third frequency.
    Type: Application
    Filed: October 28, 2002
    Publication date: April 29, 2004
    Applicant: Analog Devices, Inc.
    Inventor: Robert M. Clarke
  • Patent number: 6728870
    Abstract: In one embodiment, a programmable processor is adapted to conditionally move data between a pointer register and a data register in response to a single machine instruction. The processor has a plurality of pipelines. In response to the machine instruction, a control unit directs the pipelines to forward the data across the pipelines in order to move the data between the registers.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: April 27, 2004
    Assignees: Intel Corporation, Analog Devices, Inc.
    Inventors: Charles P. Roth, Ravi P. Singh, Gregory A. Overkamp, Ryo Inoue
  • Publication number: 20040075601
    Abstract: A switched-capacitor circuit for use in analog-to-digital conversion samples an input signal with respect to a reference voltage, without having to generate the reference voltage, by using charge redistribution. The switched-capacitor circuit prevents the need to dissipate power while producing the reference voltage. The switched-capacitor circuit is coupled to a comparator and to a logic circuit which provides control signals for switching. The switched-capacitor circuit comprises a plurality of capacitors arranged according to several embodiments.
    Type: Application
    Filed: October 16, 2002
    Publication date: April 22, 2004
    Applicant: Analog Devices, Inc.
    Inventors: Gary Carreau, Bruce Amazeen
  • Patent number: 6725360
    Abstract: An integrated circuit which has two separate paths for two different data widths. The first processing path processes data up to n bits in a n multiplier. A second path operates in parallel with the first path, and includes smaller units which process data up to n 2 bits. The two paths can operate in parallel, but since the two paths have different data widths, they can more effectively operate with the different data sizes.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: April 20, 2004
    Assignees: Intel Corporation, Analog Devices, Inc.
    Inventors: Bradley C. Aldrich, Jose Fridman, Paul Meyer, Gang Liang
  • Patent number: 6723579
    Abstract: A semiconductor wafer having a matrix array of micro-mirrors comprises a component substrate carried on a base substrate. The component substrate comprises a membrane layer in which the micro-mirrors are formed and a supporting handle layer. The base substrate comprises a base layer from which a plurality of pedestals extend upwardly therefrom into cavities in the handle layer corresponding to the micro-mirrors. Each pedestal carries electrodes for co-operating with the micro-mirrors for tilting thereof. Conductors through vias in the pedestals connect the electrodes to electrically conductive tracks on a bottom surface, and in turn through conductors through vias to addressing terminals for addressing the electrodes.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: April 20, 2004
    Assignee: Analog Devices, Inc.
    Inventors: Colin Stephen Gormley, Stephen Alan Brown, Scott Carlton Blackstone
  • Patent number: 6724239
    Abstract: A voltage boost circuit includes a boost capacitor; a charge circuit for charging in the charging mode the boost capacitor to a supply voltage, the charging circuit including a charging MOS switch interconnected between the supply voltage and one terminal of the boost capacitor and a back gate isolation circuit connected to the back gate of the charging MOS switch and including a first switch for connecting the back gate to the supply voltage for reverse biasing the back gate in the charging mode and the second switch for connecting the back gate to the one terminal of the boost capacitor for reverse biasing the back gate in the boost mode to prevent charge loss from the boost capacitor; and a boost bias voltage and a boost switch for connecting the second terminal of the boost capacitor to the boost bias voltage in the boost mode.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: April 20, 2004
    Assignee: Analog Devices, Inc.
    Inventors: Colin Price, Mark Stephen Power
  • Publication number: 20040070917
    Abstract: Switched-capacitor structures are provided that reduce distortion and noise in their processed signals because they increase isolation between structural elements and ensure that selected elements are securely turned off in one mode and quickly turned on in another mode.
    Type: Application
    Filed: June 18, 2003
    Publication date: April 15, 2004
    Applicant: ANALOG DEVICES, INC.
    Inventor: Christopher Michalski
  • Patent number: 6717995
    Abstract: A method for reducing DC offset from a receiver signal. The method includes jointly (i.e., simultaneously) estimating such DC offset and channel impulse response, and reducing the DC offset in accordance with the estimated DC offset and the estimate of the channel impulse response.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: April 6, 2004
    Assignee: Analog Devices, Inc.
    Inventor: Zoran Zvonar
  • Patent number: 6718286
    Abstract: System and method for monitoring a processor when it executes software code for a computer program. A register collects information regarding instructions executed by the processor, from the program counter; and a sampler, operatively connected to the register, asynchronously from the operation of the processor, samples contents of the register. The sampler may provide the samples to a host computer via a shift register in a JTAG port, and the host computer may provide a statistical record of the instructions executed by the processor.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: April 6, 2004
    Assignee: Analog Devices, Inc.
    Inventors: Russell L. Rivin, Lori A. Bellavance
  • Patent number: 6717470
    Abstract: A voltage amplifier circuit inhibits excessive output phase shifts from a voltage amplifier that could result in oscillation, while still providing for rail-to-rail outputs. A first output stage that includes a blocking impedance dominates the output for low output values, while a second output stage that excludes the blocking impedance dominates for higher output voltages up to rail-to-rail. The output stages are preferably implemented with CMOS transistors, with the relative sizes of the transistors and the resistance of the blocking resistor selected to enable both phase shift inhibition and rail-to-rail outputs. The first output stage provides more AC feedback, while the second output stage provides more DC feedback for high output voltages.
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: April 6, 2004
    Assignee: Analog Devices, Inc.
    Inventor: Derek F. Bowers
  • Publication number: 20040064662
    Abstract: A bus interface unit is provided for a digital signal processor including a core processor, a memory and two or more system buses for transfer of data to and from system components. The bus interface unit includes a first bus controller for receiving processor transfer requests from the core processor on two or more processor buses and for directing the processor transfer requests to the memory on a first memory bus. The bus interface further includes a second bus controller for receiving system transfer requests from the system components on the two or more system buses and for directing the system transfer requests to the memory on a second memory bus. The bus controllers may have pipelined architectures and may be configured to service transfer requests independently.
    Type: Application
    Filed: September 26, 2002
    Publication date: April 1, 2004
    Applicant: Analog Devices, Inc.
    Inventors: Moinul I. Syed, Michael S. Allen
  • Publication number: 20040064748
    Abstract: Methods and apparatus are provided for clock domain conversion in digital processing systems. The methods include operating a first circuit in a fast clock domain with a fast clock and operating a second circuit in a slow clock domain with a slow clock. To transfer signals from the fast clock domain to the slow clock domain, a first synchronization signal is asserted during each fast clock cycle in which a slow clock edge occurs. A fast signal is transferred from the fast clock domain to the slow clock domain on a fast clock edge when the first synchronization signal is asserted. To transfer signals from the slow clock domain to the fast clock domain, a second synchronization signal is asserted during each fast clock cycle that immediately follows a slow clock edge.
    Type: Application
    Filed: September 26, 2002
    Publication date: April 1, 2004
    Applicant: Analog Devices, Inc.
    Inventor: Moinul I. Syed
  • Publication number: 20040064667
    Abstract: A memory system and a method for operating a memory system are provided. The memory system includes a set of memory banks, logic for calculating a first address in each memory bank from the set of memory banks and a controller receiving a transfer address from a computing device. The controller includes logic for selecting a memory bank from the set of memory banks based on the transfer address and the first addresses of the memory banks, and for mapping the transfer address to a target address in the selected memory bank based on a first address in the selected memory bank. As a result, the set of memory banks has a contiguous memory space.
    Type: Application
    Filed: September 26, 2002
    Publication date: April 1, 2004
    Applicant: Analog Devices, Inc.
    Inventors: Thomas A. Volpe, Michael S. Allen, Aaron Bauch
  • Patent number: 6714076
    Abstract: An op amp includes a pair of buffer amplifiers interposed between the current switch and the output transistors in an output stage based on the Monticelli architecture. The buffer amps buffer the output transistors' gate capacitances, thereby allowing the output transistors to be nearly any desired size without adversely affecting the op amp's dynamic performance. This enables the op amp's compensation capacitors to set the amplifier's bandwidth, and allows the secondary pole to be at a higher frequency. The buffer amplifiers can also provide gain which effectively multiplies the transconductance of the output transistors and further extends out the secondary pole location. In addition, the buffer amplifiers can be used to provide voltage level translation between the current switch and output transistors, which can provide additional headroom for the op amp's gain stage.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: March 30, 2004
    Assignee: Analog Devices, Inc.
    Inventor: Arthur J. Kalb
  • Patent number: 6714078
    Abstract: Correction sensors and methods are provided for reduction of differential-heating signal errors along a differential signal path of an electronic circuit. An exemplary correction sensor includes first and second transistors which are coupled to different sides of the differential signal path and a differential error amplifier that couples a differential correction signal to the differential signal path in differential response to a differential error signal generated by like terminals of the first and second transistors. Bias generators are preferably included to bias at least one set of same terminals of the first and second transistors that differ from the like terminals.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: March 30, 2004
    Assignee: Analog Devices, Inc.
    Inventor: Stephen A. Cohen
  • Patent number: 6713829
    Abstract: A position sensor includes a receiver capable of receiving a position signal from an external source, and an inertial motion unit capable of sensing movement and producing a movement signal based upon the sensed movement. The position sensor also includes a processor operatively coupled with the receiver and the inertial motion unit. The processor is capable of calculating position information based on at least one of the position signal and the movement signal. Moreover, the receiver, inertial motion unit and processor are formed on a single chip.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: March 30, 2004
    Assignee: Analog Devices, Inc.
    Inventor: Maurice S. Karpman
  • Publication number: 20040051384
    Abstract: A multi channel power supply detector for selecting one of a plurality of power supplies is provided. The supply selector comprises a controller, and each channel has a switching device responsive to the controller in series with a current limiting device responsive to the controller.
    Type: Application
    Filed: September 13, 2002
    Publication date: March 18, 2004
    Applicant: Analog Devices, Inc.
    Inventors: Jane Patricia Jackson, Roger Charles Peppiette
  • Patent number: 6707407
    Abstract: A method for converting multi-bit digital video data signals to analogue form wherein the video data signals are in three formats, namely, standard definition, progressive scan and high definition formats, which permits a relatively low order analogue reconstruction filter to be used for filtering the analogue form of the signal. The three formats of the digital video data signals are over-sampled at relatively low over-sampling rates, the standard definition video signals being over-sampled at eight times the nyquist sampling frequency, the progressive scan format signals being over-sampled at four times the nyquist sampling frequency, while the high definition format signals are over-sampled at twice the nyquist sampling frequency.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: March 16, 2004
    Assignee: Analog Devices, Inc.
    Inventors: Vincent J. Troy, Anthony Scanlan, Joseph Michael Barry, John Patrick Purcell, Martin Gerard Cotter
  • Patent number: 6707403
    Abstract: An ADC (1) of balanced architecture for determining a digital word corresponding to a sampled voltage of an input signal from an input line (33) comprises a first capacitor circuit (2) comprising a most significant capacitor array (4) and a least significant capacitor array (5) which are capacitively coupled by a coupling capacitor Cc1. A second capacitor circuit (29) coupled to ground balances the first capacitor circuit (2). A differential comparator 27 compares the voltage on the first capacitor circuit (2) with that on the second capacitor circuit (29).
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: March 16, 2004
    Assignee: Analog Devices, Inc.
    Inventor: Christopher Peter Hurrell