Abstract: A method of manufacturing MEMS structures and devices that allows the fabrication of dielectric structures with improved etch selectivity and good electrical leakage characteristics. The dielectric structure includes a composite stack of silicon nitride sub-layers with a silicon-rich nitride sub-layer and a stoichiometric silicon nitride sub-layer at opposite ends of the stack. Alternatively, the dielectric structure includes a single silicon nitride layer providing a graded change in silicon content through the dielectric layer, from silicon-rich nitride to stoichiometric silicon nitride.

Abstract: A power controller circuit for a power amplifier stage includes an exponential power control circuit responsive to a power control signal for providing an exponential control current to control power amplifier stage and linear power control circuit responsive to the power control signal for supplementing the exponential control current to the power amplifier stage with a linear control current to produce a composite control current with a reduced and extended slope.

Abstract: An interface device presents a generic serial input/output (I/O) port, whose function is programmable according to a stored sequence of instructions executed by a programmable state machine. The instructions cause the programmable state machine to define operation of the serial I/O port according to a standard or other predetermined set of serial I/O communication parameters.

Abstract: A multi channel power supply detector for selecting one of a plurality of power supplies is provided. The supply selector includes a controller, and each channel has a switching device responsive to the controller in series with a current limiting device responsive to the controller.

Abstract: A memory cell array employs “source-biasing”, wherein a bias voltage is applied to the sources of one or more FETs within a memory cell to reduce their “off” state sub-threshold leakage currents. The source-bias voltage is selectively switched between a small positive bias voltage for “off” FETs, and ground for FETs which are being read. A plurality of source-bias circuits provides the selectively switched bias voltages to the memory cells in the array.

Abstract: A multi-layer vertical comb-drive actuator includes a first comb structure having a plurality of first comb fingers and a second comb structure having a plurality of second comb fingers, wherein the first and second comb fingers are substantially interdigitated. The first and second comb fingers may include two or more stacked conductive layers electrically isolated from each other by an insulating layer or an air gap. Alternatively, either the first or second comb fingers may include only one conductive layer. An application of a voltage between the first and second comb fingers causes the second comb structure to move relative to the first comb structure. The present invention includes a 2D-gimble configuration to rotate a movable element along two axis.

Abstract: Analog-to-digital converter (ADC) structures and methods are provided that reduce an initial converter nonlinearity by introducing an inverse nonlinearity into the converter's response that is substantially the inverse of the initial converter nonlinearity. In a pipelined ADC embodiment, for example,, upstream converter stages are selected that generate an upstream digital code which defines sufficient upstream code words to designate respective segments of the inverse nonlinearity. In response to each of the upstream code words, the conversion gain of the remaining downstream converter stages is then sufficiently adjusted to insert the inverse nonlinearity into the converter response.

Abstract: A method of executing an instruction stream in a pipelined execution unit of depth, p, comprises loading the instruction stream; detecting an iteration of an instruction in the loaded instruction stream; interleaving p steams of instances of the instruction in the pipeline; detecting an end of the iteration; and combining results obtained from the p streams after all programmed iterations have completed. A computational circuit comprises a register which can hold a value representing both an operand and result of an iterative operation; a multiplexer having a first input connected to receive the operand from the register, a second input connected to a source of an identify value for the iterative operation, and an output; and an operator circuit having an input connected to receive a value from the multiplexer output, and an output connected to return thee result to the register.

Abstract: Methods of protecting against a surge voltage and apparatus for performing the same. One embodiment of the invention is directed to a circuit to protect a device from a surge voltage. The circuit is connected between the device and first and second nodes to which the surge voltage may be applied. A charge storage device is connected between third and fourth nodes and the device is operatively connected to the third node and a fifth node. The circuit comprises a first overvoltage protection device coupled between the fourth node and a fifth node, the fourth and fifth nodes being operatively connected to the first and second nodes, respectively, and a second overvoltage protection device coupled between the third node and the fifth node. A voltage between the third and fifth nodes during the surge voltage is substantially less than a switching voltage of the second overvoltage protection device for at least a portion of the duration of the surge voltage.

Abstract: A digital to analog converter circuit is segmented into a main digital to analog converting unit including a plurality of current sources and a plurality of cascode units, each current source being connected to a cascode unit and a sub-digital to analog converting unit including a current source connected to a plurality of cascode units. A cascode bias unit is operatively connected to each cascode unit of the main digital to analog converting unit so as to bias each current source of the main digital to analog converting unit to operate at a same drain voltage. A second cascode bias unit is operatively connected to each cascode unit of the sub-digital to analog converting unit so as to bias the current source of the sub-digital to analog converting unit to operate at a same drain voltage. A reference voltage source is operatively connected to an input of the first cascode bias unit and connected to an input of the second cascode bias unit.

Abstract: A parallel bit correlator for recognizing a predetermined bit pattern including a predefined number m of bits in a stream of data bits including identifying successive sets of m bits in a stream of data bits and simultaneously comparing each of the sets of m bits to the predetermined bit pattern for detecting the presence of the predetermined bit pattern in the stream of data.

Abstract: A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.

Abstract: Mismatch-shaping for a digital-to-analog converter (DAC) involves allocating elements from an element array to multiple DAC channels. Various state variables are used to keep track of element usage, and the number of state variables is preferably less than the number of elements in the element array. The element array may be treated like a bi-directional circular array, in which case the array elements may be allocated to the two DAC channels as needed in opposite directions with reference to a common anchor point such that the array elements for each channel are contiguous within the circular array. All array elements are available for allocation to both DAC channels, although no array element can be allocated to both DAC channels simultaneously. A collision resolution scheme is used to prevent overlapping allocations of array elements. Pointers may be used to keep track of the array elements allocated to each channel, making implementation relatively simple.

Abstract: A circuit testing apparatus for testing a circuit under test. The circuit testing apparatus includes a controller for controlling signals being transferred between a circuit under test and the circuit testing apparatus. The circuit testing apparatus further includes a driver circuit for generating signals to be applied to the circuit under test. The driver includes a high speed slave chain and DC control loop chain coupled to the circuit under test. The high speed slave chain receives a differential voltage logic pulse train and converts the logic pulse train into a high speed current steering for producing the drive signal to be applied to the circuit under test. The DC control loop chain provides feedback paths for DC regulation of inputs of the high speed slave chain.

Abstract: A method of generating a pseudo-noise sequence without masking a linear feedback shift register (LFSR) generator is provided. An offset pseudo-noise sequence is generated at a desired offset from a reference psuedo-noise sequence by determining a corresponding initial state vector of the LFSR based on an arbitrary mask.

Abstract: An output distortion correction amplifier system includes an input stage; a current mirror connected to the input stage; an output stage having its input connected to the input stage and a current mirror and its output connected to the input stage; a compensation impedance connected to the input of the output stage; and a distortion correction circuit for directly sensing the distortion voltage across the output stage and providing to the current mirror a current representative of the distortion voltage for delivering to the compensation impedance a correction current to develop a correction voltage at the input of the output stage to nullify the effect of the distortion voltage.

Abstract: An in-situ cap for an integrated circuit device such as a micromachined device and a method of making such a cap by fabricating an integrated circuit element on a substrate; forming a support layer over the integrated circuit element and forming a cap structure in the support layer covering the integrated circuit element.

Abstract: The invention provides a power amplifier system including a plurality of amplifiers, a plurality of primary transformer windings, a single secondary transformer winding. Each of the plurality of amplifiers includes a differential input that is commonly coupled to a system input port, and each the plurality of amplifiers also includes a differential output. Each of the plurality of primary transformer windings is coupled to the differential output of one of the plurality of amplifiers. The single secondary transformer winding is inductively coupled to all of the primary transformer windings and provides a system output port to which a load may be coupled.

Abstract: A programmable input voltage range analog-to-digital converter in which a split gate oxide process allows the use of high voltage (±15 volt) switches on the same silicon substrate as standard sub-micron 5 volt CMOS devices. With this process, the analog input voltage can be sampled directly onto one or more sampling capacitors without the need for prior attenuation circuits. By only sampling on a given ratio of the sampling capacitors, the analog input can be scaled or attenuated to suit the dynamic range of the SAR (successive approximation register) ADC itself. In the system of the present invention, the sampling capacitor can be the actual capacitive redistribution digital-to-analog converter (CapDAC) used in the SAR ADC itself, or a separate capacitor array. By selecting which bits of the CapDAC or separate sampling array to sample on, one can program the input range.

Abstract: A direct conversion circuit for radio frequency signals is disclosed. The circuit includes a pair of quadrature related mixers, a phase shift unit, and a local oscillator. The pair of quadrature related mixers is coupled to a radio frequency signal input port for mixing down a radio frequency input signal. The phase shift unit is in communication with at least one of the pair of mixers for phase shifting a local oscillator signal. The local oscillator produces the local oscillator signal. The local oscillator includes a non-integer frequency multiplier for multiplying the frequency of a first voltage controlled oscillator signal by a non-integer value to produce the local oscillator signal.