Abstract: Digitally-controlled, variable-gain mixers and amplifiers are provided which couple transconductance cells to receive respective tap signals from a fixed attenuator that receives a first input signal. A gain interpolator provides first and second control currents with amplitudes that correspond to a segment of a control word and a multiplexer responds to another control-word segment by routing the control currents to a selected pair of adjacent transconductance cells. In response, the transconductance cells provide amplifier current signals which can also be routed to a transistor switch that mixes them with a second input signal to generate a mixer output signal whose amplitude corresponds to the control word.

Abstract: Improved differential amplifiers are provided for use with switched-capacitor structures. Amplifier embodiments include a differential pair of high-transconductance transistors for generation of differential currents and routing of common-mode feedback signals along an independent path so that sufficient headroom is provided for other high-transconductance transistors that generate common-mode currents. The differential and common-mode currents preferably generate differential and common-mode output signals in finite output impedances of active loads.

Abstract: A micro-machined multi-sensor that provides 1-axis of acceleration sensing and 2-axes of angular rate sensing. The multi-sensor includes a plurality of accelerometers, each including a mass anchored to and suspended over a substrate by a plurality of flexures. Each accelerometer further includes acceleration sense electrode structures disposed along lateral and longitudinal axes of the respective mass. The multi-sensor includes a fork member coupling the masses to allow relative antiphase movement, and to resist in phase movement, of the masses, and a drive electrode structure for rotationally vibrating the masses in antiphase. The multi-sensor provides electrically independent acceleration sense signals along the lateral and longitudinal axes of the respective masses, which are added and/or subtracted to obtain 1-axis of acceleration sensing and 2-axes of angular rate sensing.

Abstract: A six degree-of-freedom micro-machined multi-sensor that provides 3-axes of acceleration sensing, and 3-axes of angular rate sensing, in a single multi-sensor device. The six degree-of-freedom multi-sensor device includes a first multi-sensor substructure providing 2-axes of acceleration sensing and 1-axis of angular rate sensing, and a second multi-sensor substructure providing a third axis of acceleration sensing, and second and third axes of angular rate sensing. The first and second multi-sensor substructures are implemented on respective substrates within the six degree-of-freedom multi-sensor device.

Abstract: A micro-machined multi-sensor that provides 2-axes of acceleration sensing and 1-axis of angular rate sensing. The multi-sensor includes a rigid accelerometer frame, a first proof mass, and a second proof mass. The substrate has two associated acceleration axes in the plane of the substrate, and one associated rotation axis perpendicular to the acceleration axes. The proof masses have a common vibration axis, which is perpendicular to the rotation axis. The multi-sensor further includes a drive electrode structure for causing the proof masses to vibrate in antiphase, a first pair of acceleration sense electrode structures disposed along one of the acceleration axes, and a second pair of acceleration sense electrode structures disposed along the other acceleration axis.

Abstract: A multi-channel circuit (1) comprising three channels (CH1 to CH3), each of which is provided with a current steering DAC (5) in which crosstalk between the respective DACs (5) is minimized. Each DAC (5) comprises binary scaled current source devices (Qs1 to Qsn) and current steering switches (Qt1 and Qf1 to Qtn to Qfn) for steering currents from the current source devices (Qs1 to Qsn) to summing nodes (11,12) across which an analogue signal is developed corresponding to a digital input word. Cascode devices (Qc1 to Qcn) are provided between the respective current source devices Qs1 to Qsn and the corresponding current steering switches (Qt1 and Qf1 to Qtn and Qfn) for preventing capacitive feedthrough of voltage swings on the current steering switches (Qt1 and Qf1 to Qtn and Qfn) for minimizing crosstalk between the DACs (5).

Abstract: In an embodiment, a pipelined digital signal processor (DSP) may generate a valid bit in an alignment stage. The valid bit may be qualified in a decode stage in response to receiving a stall signal and/or a kill signal. The valid bit output from the decode stage may be stored in a latch in an address calculation (AC) stage. The valid bit may be held in the latch by a latch enable circuit in response to receiving a stall signal. The valid bit output from the latch may be qualified in the AC stage. The circuit in the AC stage including the latch, the latch enable circuit, and a valid bit qualifier may be repeated in downstream pipeline stages, for example, the execution stages.

Abstract: A logic isolation circuit has a transmitter circuit for receiving a logic input signal and providing a periodic signal to an isolation barrier, and a receiving circuit for receiving the periodic signal from the isolation barrier and for providing an output signal that indicates the transitions in the logical input signal.

Abstract: Image sensors are provided that reduce conflicts between different sensor functions because sensor structures do not demand access to the same internal spaces. Accordingly, sensor structures can be independently arranged to enhance their respective functions. In particular, sensor embodiments include a substrate, semiconductor devices and an interconnect structure carried over the substrate, reference and sense electrodes and a photoconductive medium that are carried over the interconnect structure, and vias that couple the reference and sense electrodes to the interconnect structure and semiconductor devices. Different sensor elements do not demand access through the same internal VLSI spaces and may thus be arranged to enhance their respective sensor functions. In addition, sensors of the invention will respond to radiation rays that are orthogonal to the sensor's upper face and also to radiation rays that are tilted from this relationship.

Abstract: A frequency acquisition system for a tunable oscillator is provided that generally includes a frequency-locked loop circuit including a detector system, responsive to the frequency of an output signal of a tunable oscillator and the frequency of a reference signal, to provide a digital output signal representative of a difference in frequency between the output signal and the reference signal, a register circuit for storing a value representative of the present control state of the tunable oscillator; and an accumulator circuit responsive to a value representative of the present control state of the tunable oscillator and to the digital output signal for providing an updated value for adjusting the frequency of the tunable oscillator towards the frequency of the reference signal.

Abstract: A test mode control circuit for reconfiguring a device pin of an integrated circuit chip which is initially configured in a test mode includes an input register for applying trim/configuring data to one or more components on an integrated circuit chip; a device pin; an output register for receiving output data from an integrated circuit on an integrated circuit chip which integrated circuit has had one or more of its elements trimmed/reconfigured; an I/O logic circuit for controlling the device pin to operate as a test pin to selectively deliver the trim/configuring data to the input register and receive output data form the output register; a programmable ray including a plurality of logic state elements for permanently mapping a selected set of the trim/configuring data from the input register, the programmable array including a test bit; and a switching system for applying the trim/configuring data to the one or more components on the integrated circuit when the test bit is in a first, test mode and for ap

Abstract: A method for forming a multi-layer semiconductor device (1) having a lower silicon layer (4), an intermediate silicon layer (5) within which micro-mirrors (10) are formed and an upper spacer layer (6) of silicon for spacing another component from the micro-mirrors (10). First and second etch stop layers (8,9) of oxide act as insulation between the respective layers (4,5,6). In order to minimize damage to the micro-mirrors (10), the formation of the micro-mirrors (10) is left to the end of the forming process. An assembly of the lower layer (4) and the intermediate layer (5) with the first etch stop layer (8) is formed, and the second etch stop layer (9) is then grown and patterned on the intermediate layer (5) for subsequent formation of the micro-mirrors (10). The upper layer (5) is then bonded by an annealing process to the patterned second etch stop layer (9).

Abstract: Described is a differential clock receiver comprising a converter, a differential input stage, and a differential output stage. The converter converts a control signal indicative of a timing relationship into a DC offset signal. The differential input stage receives a differential clock signal and the DC offset signal. The differential input stage generates an intermediary differential signal from the differential clock. The intermediary differential signal has a DC offset resulting from the DC offset signal. The differential output stage receives the intermediary differential signal and generates at least two output signals from the intermediary differential signal. The output signals have a timing relationship determined by the DC offset of the intermediary differential signal.

Abstract: Methods and apparatus are provided for branch prediction in a digital processor. A method includes providing a branch target buffer having a tag array and a data array, wherein each entry in the tag array provides an index to a corresponding entry in the data array, storing in a selected entry in the tag array information representative of a branch target of a current branch instruction, storing in a corresponding entry in the data array information representative of a branch target of a next branch instruction, and providing the information representative of the branch target of the next branch instruction in response to a match to an entry in the tag array. The information representative of the branch target of the next branch instruction may include a taken branch target address of the next branch instruction and an offset value. The offset value may represent an address of a next sequential instruction following the next branch instruction.

Abstract: A counter circuit is provided which is particularly suitable for controlling cyclical events. The counter consists of a chain of logic elements 160, 167, 164 which sequentially pass a ‘1’ along the chain in response to a clock signal. Each element is also responsive to a respective select signal and, if selected, behaves like a latch, whereas if unselected it behaves as if it were not there.

Abstract: An integrated convective accelerometer device. The device includes a thermal acceleration sensor having a thermopile and a heater element; control circuitry for providing closed-loop control of the thermopile common-mode voltage; an instrumentation amplifier; clock generation circuitry; voltage reference circuitry; a temperature sensor; and, output amplifiers. The device can be operated in an absolute or ratiometric mode. Further, the device is formed in a silicon substrate using standard semiconductor processes and is packaged in a standard integrated circuit package.

Abstract: In one embodiment, a method is disclosed for holding instruction fetch requests of a processor in an extended reset. Fetch requests are disabled when the processor undergoes a reset. When the reset is completed, fetch requests remain disabled when the instruction memory is being loaded. When loading of the instruction memory is completed, fetch requests are enabled.

Abstract: A programmable frequency synthesizer including a voltage-controlled oscillator, a regenerative frequency divider and a programmable integer divider, that provides wideband frequency coverage from a single narrowband oscillator. The voltage-controlled oscillator may generate a first signal having a first frequency. The regenerative frequency divider is coupled to the voltage-controlled oscillator and receives the first signal and performs a fractional multiplication of the first frequency of the first signal to provide a second signal a having a second frequency. The programmable integer divider is coupled to the regenerative frequency divider, and receives the second signal and divides the second frequency by a predetermined integer to provide a third signal having a third frequency.

Abstract: In an embodiment, an address pipeline corresponding to an instruction pipeline in a processor, for example, a digital signal processor (DSP), may generate and track the instruction address of each instruction at each stage. The address pipeline may include program count (PC) generation logic to automatically calculate the PC of the next instruction based on the width of the current instruction for sequential program flow. The address pipeline may also track valid bits associated with each instruction and store the address of the oldest valid instruction for return to the original program flow after a disruptive event.

Abstract: An amplifier circuit and fabrication method including a bias input node, an RF input node, an RF output node, and a plurality of amplifier cells. Each cell has a plurality of discrete emitter contacts of a first conductivity type, a plurality of discrete base contacts of a second conductivity type and grouped in two or more groups, at least one collector contact of the first conductivity type connected to the RF output node, and a base capacitor for each group having two electrodes: an input electrode coupled to the RF input node and an output electrode coupled to a group of discrete base contacts. There is also a base resistor for each group having an input coupled to the bias input node and an output coupled to a group of discrete base contacts. An emitter resistor is coupled to each discrete emitter contact to provide more effective base ballasting and thermal stability than with a cascode arrangement of HBT transistors.