Abstract: An N-phase switching voltage regulator includes N current sensing elements which carry respective phase currents. The voltages present at the switch node sides of the sensing elements are summed and presented to an amplifier which also receives the regulator's output voltage, to produce an output which is proportional to the regulator's total output current Iout. The invention also provides a means for direct insertion of total inductor output current information into a regulator's voltage-mode control loop, to provide active voltage positioning (AVP) for the output voltage. A voltage based on total inductor output current is summed with the regulator's reference voltage; this sum and Vout are applied to the voltage control error amplifier, the output of which is processed to operate the regulator's switches. This enables the regulator's output to have a desired droop impedance and to provide AVP of Vout as a function of total filtered inductor output current Iout(fltr).

Abstract: Methods and apparatus are provided for transferring data words from a source to a destination. The apparatus includes a datapath buffer coupled by a first data bus to the source and coupled by a second data bus to the destination, write control logic for writing a first number of data words in the datapath buffer in response to a first source transfer condition and for writing a second number of data words in the datapath buffer in response to a second source transfer condition, and read control logic for reading the first number of data words from the datapath buffer in response to a first destination transfer condition and for reading the second number of data words from the datapath buffer in response to a second destination transfer condition.

Abstract: A hiccup-mode short circuit protection circuit and method for a linear voltage regulator using a FET pass transistor uses the capacitance of the pass transistor's gate as a timing element. The regulator's output voltage is monitored, and when it droops below a voltage indicative of a short-circuit condition, the regulator's drive signal is disconnected from the pass transistor. While the short-circuit condition persists, a first current is provided to charge the pass transistor's gate capacitance. When the gate voltage rises above a first predetermined threshold, a second current is provided to further charge the gate capacitance. When the gate voltage rises above a second predetermined threshold, the gate capacitance is discharged. The gate capacitance is cyclically charged and discharged in this way unless the output voltage rises to indicate that the short-circuit condition has cleared, in which case the regulator's drive signal is restored to the pass transistor's gate.

Abstract: A method for placing a device in a reduced power-consumption mode of operation. The method comprises the steps of initializing a device select signal into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first predetermined time window. A device is also described that includes means for detecting logic state transitions at a device select input and a clock input, and means for changing operating mode of the device in response to a predetermined number of logic state transitions at the clock input, occurring between logic state transitions at the device select input.

Abstract: An interface circuit (1) for facilitating communication between an integrated circuit (2) and an external device (not shown) in either SPI protocol or one or both of I2C and SMBus protocols, comprises a signal processing circuit (7), which is configurable in I2C/SMBus and SPI protocol modes, and four communication terminals, namely, a CLK pin (3), and ADD/DOUT pin (4), and SDA/DIN pin (5) and a {overscore (CE)} pin (6). On power-up of the interface circuit (1) the signal processing circuit (7) is configured in I2C/SMBus protocol mode by a first mode select signal (Vdd) applied to a mode select input port (10) by a multiplexer (15) in response to a logic low switch signal from a switch signal flip-flop (22). A first state machine (20) outputs a logic low signal to an AND gate (21) for so long as the {overscore (CE)} pin (6) remains continuously high or low, thus holding a reset input of the switch signal flip-flop (22) low.

Abstract: A circuit testing apparatus includes a controlling processor for controlling stimulus signals to be applied to a circuit under test and for processing and storing response signals generated by the circuit under test in response to the stimulus signals. The stimulus signals are generated by a driver portion of a receiver/driver circuit coupled to a pin on the circuit under test. The driver includes an output stage circuit coupled to the pin on the circuit under test. The output stage circuit includes a linear amplifier circuit which receives a control signal via the controlling processor and generates from the control signal a drive signal to be applied to the circuit under test. The linear amplifier allows the driver to produce a drive signal with a high level of voltage and timing accuracy and, in the case of digital square pulse signals, a high level of pulse symmetry.

Abstract: A current mirror replica biasing system where the resistor-programmable base current of a current reference transistor is accurately and scalably mirrored and input to the base of an output transistor, the current provided by the output transistor being useful as bias current to a load circuit, including a current reference transistor and an output transistor of like polarity; a pair of bipolar transistors, of like polarity to each other and opposite polarity to the current reference transistor and output transistor, arranged as a current mirror to mirror the base current of the current reference transistor, which base is exclusively interconnected to the input of the current mirror; and a current source to establish a desired reference current in the current reference transistor; wherein variations in the current source circuitry can result in circuit performance of the current mirror replica biasing system that is proportional to absolute temperature, or other desired function.

Abstract: A programmable non-volatile data storage calibration circuit stores a calibration code for a temperature sensor circuit of an IC, comprising a programmable array of addressable bi-state, bi-stable first circuit elements each comprising a fusible resistor. A power supply controlled by a data input signal addresses the first circuit elements to be switched from a first to a second state in the fusible resistor state, the supply, and a clock signal applied to an I/O terminal clocks the data input signal to the interpreter circuit. The interpreter circuit sequentially selects and addresses the first circuit elements and enables switching of the first circuit elements when the supply voltage is at its maximum, blowing a selected fusible resistor. A second, similar circuit element is switched to its second state after programming the calibration circuit to prevent its further programming.

Abstract: A novel optical path switching system, architecture and technique wherein light beam data traffic is to be switched by MEMS mirrors between source and destination nodes, and test ports are used to set up optical paths even before the real data traffic is propagated, with a combination of an electrical mirror-sensing feedback loop for controlling coarse mirror positioning, and an optical path power-sensing feedback loop for controlling fine adjustments in the mirror position.

Abstract: A multi-stage integrator achieves a relatively high small-signal gain, broad bandwidth, and very clean transient pulse response. Only simple inverters are used, making the design scalable to deep sub-micron with low supply voltages, a rail-to-rail output swing, and a relatively low output impedance and useful tolerance to capacitive loading. A high gain amplifier is coupled between an integrator input node and amplifier output node. A broadband transconductor is coupled between the integrator input node and integrator output node. A resistor connects the amplifier output node and the integrator output, while a capacitor is coupled from the integrator input to the amplifier output. The conductance of the resistor (the reciprocal of the resistance, or 1/R) is selected to be substantially equal to the transconductance gm of the transconductor. A method for achieving clean transient pulse response is also described.

Abstract: A method and apparatus for measuring and controlling the phase difference or time difference between two signals is presented. In some embodiments two sample and hold (S/H) circuits are arranged as a cooperating system that alternately samples a first signal using the second as a reference. Chopping may be used at the input or output of the S/H circuits. In some embodiments, accurate measurement of digital signal phase differences, such as between two square waves, is obtained without the problems associated with traditional pulse-generation techniques that fail at high frequencies and short pulse lengths.

Abstract: Line drivers are provided that are suitable for driving communication cables (e.g., in Data Over Cable Service Interface Specification (DOCSIS) certified systems) without the need for output drivers and their size, power-consumption, noise and signal-distortion penalities. These line drivers directly couple switched current mirrors to a transformer's input winding to simultaneously provide currents in response to a differential input signal and a digital command signal and drive the load impedance to thereby realize a corresponding signal gain.

Abstract: A dual channel ADC uses two digital to analog converters (DACs) and a single comparator to convert two analog input channels. One DAC is used for successive approximation, while the other DAC is used for calibration. The dual channel ADC allows for sampling and conversion of single-ended, pseudo-differential, and fully differential analog input signals while maintaining layout symmetry and reducing crosstalk without substantially increasing circuit area. The single comparator is used for converting both analog input channels. Additional logic (such as switches or digital logic) is used to connect the input sampling capacitors and DACs to the appropriate inputs of the comparator for converting the analog input channels.

Abstract: This invention discloses a process for forming durable anti-stiction surfaces on micromachined structures while they are still in wafer form (i.e., before they are separated into discrete devices for assembly into packages). This process involves the vapor deposition of a material to create a low stiction surface. It also discloses chemicals which are effective in imparting an anti-stiction property to the chip. These include polyphenylsiloxanes, silanol terminated phenylsiloxanes and similar materials.

Abstract: A wideband impedance attenuator includes a phase-locked loop filter, a voltage-controlled oscillator connected to the phase-locked loop filter during transmit, and an impedance circuit connected to the phase-locked loop filter and the voltage controlled oscillator. The impedance circuit is a scaled version of the phase-locked loop filter. Moreover, the wideband impedance attenuator attenuates a Gaussian frequency shift key modulation signal by a factor of 1/(N+1) using the impedance circuit, which has an impedance of N*Z(s), and the phase-locked loop filter, which has an impedance of Z(s). An output frequency is generated using a voltage-controlled oscillator wherein the output frequency corresponds to the attenuated Gaussian frequency shift key modulation signal. In addition, a comparator compares a voltage of an output from the programmable gain amplifier with a voltage necessary to produce a predetermined frequency shift in a voltage-controlled oscillator to produce a gain signal.

Abstract: Methods and apparatus are provided for use in digital information processors that support digital memory buffers. In one aspect of the present invention, a digital signal processor receives a swap instruction and responds to the swap instruction by swapping the contents of a first address register and a second address register. In another aspect, a digital signal processor receives a swap instruction, swaps the contents of a first address register and a second address register in a future file, generates and sends one or more control signals to an architecture file in a downstream stage of a pipeline in response to the swap instruction, and swaps the contents of the first address register and the second address register in the architecture file in response to the one or more control signals.

Abstract: One embodiment of the invention is directed to a method comprising an act of generating a timing signal, wherein at least some rising edges of the timing signal are based on edges of a first delay signal having a first period and a first phase, and at least some falling edges of the timing signal are based on edges of a second delay signal having a second period that is substantially the same as the first period, and a second phase that is different from the first phase. Another embodiment of the invention is directed to a programmable clock synthesizer comprising an edge-triggered circuit that receives a rising edge delay signal and a falling edge delay signal, wherein the edge-triggered circuit is adapted to generate a synthesized clock signal having rising edges triggered in response to edges of the rising edge delay signal and falling edges triggered in response to edges of the falling edge delay signal.

Abstract: One embodiment of the invention is directed to a method, comprising acts of generating a plurality of delay signals, and processing at least first and second delay signals of the plurality of delay signals to generate a first timing signal. Another embodiment of the invention is directed to a timing signal generator to generate a plurality of timing signals. The circuit comprises a delay signal generator to generate a plurality of delay signals, and a clock synthesizer to generate the timing signals based on selected ones of the delay signals.

Abstract: A successive approximation routine analog-to-digital converter includes a switched-capacitor circuit that samples an input voltage into a plurality of capacitors without the need for power to be dissipated by the analog-to-digital converter. A comparator, coupled to the switched-capacitor circuit, compares a voltage across the capacitors with another voltage during each of a number of iterations. A common mode voltage of the switched-capacitor circuit is boosted during at least some of the iterations. The boost may be accomplished in many different ways and may be different for each of a single-ended, a quasi-differential and fully differential versions of the analog-to-digital converter.

Abstract: In one embodiment, a pipelined processor includes a reset unit that provides an output reset signal to at least one stage of the pipeline. The reset unit is adapted to detect at least a hard reset request, a soft reset request and an emulation reset request. The pipeline comprises N stages and the reset unit asserts the reset signal for at least N cycles of a clock after the reset request has been cleared. Each stage if the pipeline has a storage circuit for storing a corresponding valid bit. At least one of the storage circuits is cleared in response to the reset signal. In addition, the reset unit handles the reset request as a reset event having an assigned priority.