Abstract: A PLL frequency multiplier is provided having a latency substantially equal to the wake-up time of the PLL. An operative clock signal is provided to a processor while the PLL is acquiring phase lock by ensuring that the clock signal does not contain frequencies above a target frequency of a PLL and below a predetermined threshold frequency. In particular, a frequency divider and a frequency detector are provided to prevent the frequency of the clock signal from operating outside the range defined by the threshold and target frequencies.

Abstract: A micro-machined multi-sensor that provides 1-axis of acceleration sensing and 2-axes of angular rate sensing. A method of fabricating the micro-machined multi-sensor includes depositing a layer of sacrificial material or structural material onto the substrate surface. The deposited layer of sacrificial or structural material is then masked with a predetermined mask pattern formed using a rectilinear grid having multiple horizontal and vertical spacings. The mask pattern defines the functional components of the sensor device. In the event the multi-sensor includes at least one functional component whose alignment on the substrate is critical to the optimal performance of the sensor, the critical component is defined so that its longitudinal axis is substantially parallel to the horizontal or vertical axis of the mask.

Abstract: A method and apparatus for synchronizing actions of two circuits or two parts of one circuit where each circuit utilizes a different clock signal are presented. In some embodiments, more than one clock signal are derived from a master clock signal and run at the same frequency but have an unknown or variable phase difference. Some aspects of the invention solve the problem of coupling two clocked circuits where synchronization is required to properly read or sample a signal from a data line connecting the two circuits. In some embodiments, an error window is defined during which sampling is suppressed, for example to avoid sampling during data transitions. One embodiment involves time shifting a pseudo-signal to generate two time-shifted signals and then defining the error window as the time during which the two time-shifted signals differ from one another.

Abstract: A Galois field multiplier system includes a multiplier circuit for multiplying two polynomials with coefficients over a Galois field to obtain their product; a Galois field linear transformer circuit responsive to the multiplier circuit for predicting the modulo remainder of the polynomial product for an irreducible polynomial; and a storage circuit for supplying to the Galois field linear transformer circuit a set of coefficients for predicting the modulo remainder for predetermined irreducible polynomial.

Abstract: In one embodiment, a programmable processor is arranged to include early registers to support hardware loops. In this manner, a system may increase processing speed without significantly increasing power consumption. Loop conditions of a loop may be loaded into a set of early registers. These conditions may then be detected from the early registers before the loop conditions are written to a set of architectural registers.

Abstract: An accelerometer had a movable electrode between two fixed electrodes to form a differential capacitor. Drivers provide AC drive signals to the fixed electrodes. The movable electrode is coupled through reading circuitry to an output terminal. In response to a sensed acceleration, feedback is provided from the output terminal to one or both drivers to null any AC signal on the movable electrode and to keep the electrostatic forces between the movable electrode and each of the fixed electrodes equal.

Abstract: In an embodiment, a processor may be operable in a user mode and in a supervisor mode. The processor may initialize hardware loops in the user mode by loading a top instruction address in a LOOP_TOP register and a bottom instruction address in a LOOP_BOT register.

Abstract: A wafer cap protects micro electromechanical system (“MEMS”) structures during a dicing of a MEMS wafer to produce individual MEMS dies. A MEMS wafer is prepared having a plurality of MEMS structure sites thereon. Upon the MEMS wafer, the wafer cap is mounted to produce a laminated MEMS wafer. The wafer cap is recessed in areas corresponding to locations of the MEMS structure sites on the MEMS wafer. The capped MEMS wafer can be diced into a plurality of MEMS dies without causing damage to or contaminating the MEMS die.

Abstract: In an embodiment, a system may include a processor that handles a number of events. These events may include general purpose interrupts (GPIs) assigned to particular devices in the system. Addresses for event service routines appropriate for particular events may be stored in an event vector table (EVT). In a system with a number of devices that utilize the processor's resources, some interrupts may be overloaded, that is, assigned to more than one device. If an overloaded interrupt occurs, the processor may override the EVT entry and select an address supplied by a system controller at a set of reset vector pins.

Abstract: An electronic meter includes a sensing circuit for sensing voltage and current values of a waveform, an analog-to-digital converter for converting the sensed voltage and current values to digital voltage and current values, a digital filter for delaying one or both of the digital voltage and current values to compensate for a phase shift error in the sensing circuit, and a computation circuit for computing one or more parameters of the waveform in response to the phase compensated voltage and current values. The electronic meter may be calibrated by applying to the meter a test waveform having a known phase shift, measuring the phase shift using the electronic meter, determining a phase shift error based on the difference between the known phase shift and the measured phase shift and determining digital filter coefficients to produce a digital filter delay that corresponds to the phase shift error.

Abstract: In one embodiment, a modulo addressing unit for a processor is described that includes a plurality of adders to generate an uncorrected target module address and at least one corrected target module address in parallel. A comparator selects one of the target module addresses a function of a base address (b) for a circular buffer, a length (L) of the circular buffer, an index address (I) and a modifier value (M). In one embodiment the comparator selects a first corrected target module address when I+M<B, a second corrected target module address when I+M>=B+L and an uncorrected module address when B<=I+M<B+L.

Abstract: Methods and structures are provided for interleavably processing data signals and error signals in alternating first and second operational phases of successive converter stages of pipelined analog-to-digital converter systems. In particular, converter stages are arranged to interleavably process data signals and error signals in alternating first and second operational phases as they convert input data signals to corresponding digital code. The interleaved methods and structures significantly reduce conversion errors caused by less-than-infinite gain A of converter stage amplifiers. Because this performance enhancement is realized primarily with existing pipelined structure, modification complexity and cost of conventional pipelined systems is substantially reduced. The advantages of the invention are also realized with minimal increase in power consumption and circuit space.

Abstract: An a.c. coupled multistage high gain operational amplifier includes at least two gain stages, each having an input and an output; an a.c. coupling level shifting capacitance interconnecting the output of a first stage to the input of a second stage; and a charging circuit interconnecting with the a.c. coupling level shifting capacitance and the input of the second stage to charge the a.c. coupling level shifting capacitance in a track phase and to connect the a.c. coupling capacitance to the input of the second stage during a hold phase for dissociating the bias voltages of the stages.

Abstract: A microwave directional coupler includes a first transmission line having an input port and an output port, and a second transmission line having a coupled port and a terminated port. The second transmission line is electromagnetically coupled to the first transmission line. A first capacitor is coupled between the input port and a reference potential, such as ground, a second capacitor is coupled between the output port and the reference potential, a third capacitor is coupled between the coupled port and the reference potential, a fourth capacitor is coupled between the terminated port and the reference potential, and a fifth capacitor is coupled between the output port and the terminated port. The microwave directional coupler has a small size in comparison with prior art directional couplers.

Abstract: Variable-gain amplifiers (VGAs) are provided that realize gain accuracy (e.g., over variations in temperature and fabrication processes) while also providing this accuracy over a wide bandwidth and without the signal-to-noise degradation typically associated with signal attentuating elements. Differential signal and gain amplifiers of these VGAs include current sources which are controlled by a common error signal Serr. The gain amplifier is supplemented by feedback structure that generates the error signal Serr and controls the amplifier's transconductance to be the ratio of at least one of currents and resistors. Because such ratios can be well matched (especially in integrated circuit realizations of the variable-gain amplifiers) and because the current source of the signal amplifier is also controlled by the error signal Serr, this wide-band, low-noise open-loop amplifier's gain is accurately controlled.

Abstract: In an embodiment, a pipelined digital signal processor (DSP) may generate a valid bit in an alignment stage. The valid bit may be qualified in a decode stage in response to receiving a stall signal and/or a kill signal. The valid bit output from the decode stage may be stored in a latch in an address calculation (AC) stage. The valid bit may be held in the latch by a latch enable circuit in response to receiving a stall signal. The valid bit output from the latch may be qualified in the AC stage. The circuit in the AC stage including the latch, the latch enable circuit, and a valid bit qualifier may be repeated in downstream pipeline stages, for example, the execution stages.

Abstract: A grayscale reference generator provides correction voltages to respective connection points on a source driver which drives an array of LCD pixels, to compensate for pixel non-linearity. The generator includes a number of DACs equal to the number of correction voltages. In a preferred embodiment, an analog multiplexer connected between the DACs and the source driver's connection points selectively connects the DAC outputs to the connection points so that the source driver produces the necessary pixel drive voltages as the voltage polarity across the pixels is periodically reversed.

Abstract: A memory cell array employs “source-biasing”, wherein a bias voltage is applied to the sources of one or more FETs within a memory cell to reduce their “off” state sub-threshold leakage currents. The source-bias voltage is selectively switched between a small positive bias voltage for “off” FETs, and ground for FETs which are being read. A plurality of source-bias circuits provides the selectively switched bias voltages to the memory cells in the array.

Abstract: “A compensating circuit for use in a switch circuit comprising scaled current steering switches, a switch circuit comprising the compensating circuit, and a method for minimising time-skew in switching scaled current steering switches” An eight bit current steering DAC comprising scaled current steering switches (ST0,SF0,ST(n−1),SF(n−1)) (where n=8) comprises a comprising plurality of compensating MOS switches (SCT0 and SCF0 to SCT(n−1) for minimising time-skew when switching selected ones of the current steering switches from one state to another. The compensating switches (SCT,SCF) are of type similar to the current steering switches (STi and SFi), and are sized so that the combined switching load presented to the corresponding driver circuit (Di) by the sum of the parasitic load capacitance of the current steering switch (STi or SFi) and the corresponding compensating switch (SCTi or SCFi) is substantially similar for each driver circuit (Di).

Abstract: In one embodiment, a programmable processor is configured to support a loop setup instruction. The loop setup instruction may be decoded and a zero offset loop may be detected from the loop setup instruction. The next instruction in the instruction stream may then be immediately issued as a first instruction in a loop. The loop setup instruction may also be used to detect a single instruction loop.