Abstract: A transceiver circuit is disclosed for use in radio frequency communication systems. The circuit includes a transmitter circuit, a receiver circuit and a local oscillator circuit. The local oscillator circuit includes at least one oscillator input signal having a frequency that is a non-integer multiple of the transmission frequency of the radio frequency communication system. The oscillator input signal is used to produce a transmitter local oscillator signal and a receiver local oscillator signal.

Abstract: A circuit including at least one low voltage input, at least one high voltage output, and a field transistor having a source, a drain and a control region. The circuit may comprise a high-voltage amplifier. In this embodiment, an electrical connection between the high-voltage output terminal and the field transistor control region, and an electrical connection between the input terminal and a second transistor. Various embodiments of the field transistor are described.

Abstract: A power metering system including a first modulator receiving a first analog voltage associated with a current and outputting a first digitized signal. A second modulator receives a second analog voltage and outputs a second digitized signal. A first lowpass filter filters out high frequency noise associated with the first signal and decimates the frequency of the first digitized signal. The first lowpass filter outputs a first filtered signal. An interpolator performs up sampling of the signal associated with the first filtered signal. The interpolator outputs a first up sampled signal. An integrator integrates the first up sampled signal. The integrator outputs an integrated signal. A first multiplier multiplies the second digitized signal and integrated signal, and outputs a multiplied signal. The multiplied signal being used to measure power.

Abstract: Simple, inexpensive waveform generators and methods are provided that generate curvilinear waveforms which comprise a fundamental sinusoid and harmonics that are either absent or are significantly reduced from the fundamental. In an exemplary method, a generator converts a first straight-line waveform into a level-shifted, frequency-doubled second straight-line waveform, multiplies the straight-line segments of the first and second waveforms to provide a first curvilinear waveform, and sums this curvilinear waveform with a scaled version of the first straight-line waveform to realize a second curvilinear waveform with further-reduced harmonics.

Abstract: High-speed differential amplifiers are provided for use with switched-capacitor structures. These amplifiers reduce current demand during small-signal operation and generate high slew currents during large-signal operation. These processes are realized with slew-current generation structures that directly generate slew currents during large-signal operation and thus avoid the degradation of intermediate current-genration structures.

Abstract: Buffer amplifiers are provided with a replica current generator that supplements a buffer transistor and is configured to provide a replica current which substantially equals required load currents in the amplifier's output load. Because the current of the buffer transistor remains constant, its base-emitter voltage Vbe remains constant and the amplifier linearly reproduces the input signal Sin across the output load.

Abstract: Analog-to-digital converter (ADC) structures and methods are provided that reduce an initial converter nonlinearity by introducing an inverse nonlinearity into the converter's response that is substantially the inverse of the initial converter nonlinearity. In a pipelined ADC embodiment, for example, upstream converter stages are selected that generate an upstream digital code which defines sufficient upstream code words to designate respective segments of the inverse nonlinearity. In response to each of the upstream code words, the conversion gain of the remaining downstream converter stages is then sufficiently adjusted to insert the inverse nonlinearity into the converter response.

Abstract: An image processor that calculates values that are related to distortion between two image parts. The values are detected in a previous calculation. Those values are then used in the next calculation cycle to detect an early exit. That value, called least, divided by the number of accumulators, and its negative is loaded into the accumulators. When the accumulators reach zero, an early exit is established.

Abstract: A system and method are provided for controlling the on/off timing relationship between two transistors in a differential that are connected at a tail node to a common current generator. The on/off timing relationship is controlled by on/off signals that control the state of the transistors such that one transistor turns one while the other is turning off. An overlap signal is derived from the tail node excursion and is indicative of whether the on/off signals are overlapping too much or too little. A control signal is generated based on the overlap signal. The timing of driver signals used to derive the on/off signals is adjusted based on the control signal. When more overlap is needed, the timing of the driver signals is adjusted such that there is more overlap of the derived on/off signals. When less overlap is needed, the timing of the driver signals is adjusted such that there is less overlap of the derived on/off signals.

Abstract: A method and apparatus for synchronizing actions of two circuits or two parts of one circuit where each circuit utilizes a different clock signal. More than one clock signal are derived from a master clock signal and run at the same frequency but have an unknown or variable phase difference. The invention solves the problem of coupling two clocked circuits where synchronization is required to properly read or sample a signal from a data line connecting the two circuits. An error window is defined during which sampling is suppressed, for example to avoid sampling during data transitions. The method of apparatus involves time shifting a pseudo-signal to generate two time-shifted signals and then defining the error window as the time during which the two time-shifted signals differ from one another.

Abstract: A circuit for matching a first mirror transistor with a second mirror transistor in a current mirror includes a bias transistor and a diode connected transistor to match such mirror transistors. More particularly, the circuit is a part of an amplifier having an output with a quiescent voltage and at least one rail voltage. The first mirror transistor has a first terminal coupled to the output and a second terminal coupled to the at least one rail voltage. To effectuate its mirroring function, the bias transistor is coupled to a first terminal of the second mirror transistor, and the diode connected transistor is coupled to both a second terminal of the second mirror transistor and the at least one rail voltage. The bias transistor has a terminal with a quiescent voltage that is substantially equal to the quiescent voltage of the output.

Abstract: A timing vernier applies a pair of stable bias voltages to intermediate points of an impedance string to establish reliable and calibratable delay cell biases for a fine multiplexer. A coarse input multiplexer is switched to a new timing signal substantially immediately after passing a prior valid timing signal to maximize the time prior to each valid output that the waveform is independent of the prior delay pattern. Logic circuitry is provided for three different phase differential regimes between successive timing signals to ensure that invalid output signals separated by less than a clock period are not produced. Mask commands are inserted into a series of timing control commands to equalize the average rates of writing and reading out the timing control commands with the mask commands skipped at readout.

Abstract: High-speed differential amplifiers are provided for use with switched-capacitor structures. These amplifiers reduce current demand during small-signal operation and generate high slew currents during large-signal operation. These processes are realized with slew-current generation structures that directly generate slew currents during large-signal operation and thus avoid the degradation of intermediate current-genration structures.

Abstract: Parallel analog-to-digital converter systems are provided in which converters are temporally interleaved. In particular, converters are partitioned into at least two converter groups which are assigned different respective group converter periods that are multiples of the system periods. With converters in each of the converter groups, respective samples are processed over that group's respective group converter period and the group converter periods of all converters are temporally shifted to process each of the samples with at least one of the converters.

Abstract: A relatively high speed circular memory device, in combination with other processes, improves image processing efficiency. To that end, a method and apparatus of processing image data stored in an initial memory logically divides the image into a plurality of contiguous strips. A first plurality of the strips are stored in a working memory having a circular addressing arrangement, where the working memory is faster than the initial memory and has a plurality of sequential address locations. The first plurality of strips are contiguous and have a start address. In addition, the first plurality of strips are stored in the working memory in a contiguous manner, and processed through the working memory relative to the start address.

Abstract: A level translating digital switch in which a switching element provides switching and level translation between a first system and a second system that operate using different logic supply voltages. In a situation where the supply voltage for the first system is larger than the supply voltage for the second system, the switching element is driven by a voltage lower than the logic supply voltage of the first system.

Abstract: A passive matching network is connected to an input/output line for an automatic test equipment drive channel to compensate for capacitances associated with a receiver circuit connected to the line, and also an optional current-mode driver circuit. The matching circuit preferably comprises a T-coil circuit that can include a bridging capacitor; separate T-coil circuits can be provided to separately compensate for receiver circuit and current-mode driver circuit capacitances. The driver and receiver circuits can be implemented on a common layer of an integrated circuit, with the T-coil windings implemented in a separate layer of the same integrated circuit that is spaced from the common layer by at least one dielectric layer.

Abstract: An integrated circuit is provided in which a scan controller for controlling a scan test is integrated within the integrated circuit and shares the same input pins as a serial programmable interface of the integrated circuit.

Abstract: A packaged microchip has a stress sensitive microchip having a microchip coefficient of thermal expansion, a package having a package coefficient of thermal expansion, and an isolator having an isolator coefficient of thermal expansion. The isolator is connected between the stress sensitive microchip and the package. The microchip coefficient of thermal expansion illustratively is closer to the isolator coefficient of thermal expansion than it is to the package coefficient of thermal expansion.

Abstract: Methods and devices for code independent switching in a digital-to-analog converter (DAC) are described. A synchronous digital circuit is triggered by a clocking signal and develops a digital data signal. A current steering circuit has a common source node for supplying current, and develops an analog output signal representative of the digital data signal. Any switching disturbances at the common source node are substantially data independent.