Abstract: An offset correction circuit loop with summing nodes, a variable gain transconductance amplifier and capacitor. The input to the loop is sent to a first summing node and then to a separate circuit. The output of the separate circuit is sent to the output of the loop and to the input of a second summing node. The second summing node subtracts the circuit output from a reference voltage and sends the result to the transconductance amplifier which outputs a corrective current which is then integrated onto the capacitor to produce a corrective input offset voltage estimate.

Abstract: An N-phase switching voltage regulator includes N current sensing elements which carry respective phase currents. The voltages present at the switch node sides of the sensing elements are summed and presented to an amplifier which also receives the regulator's output voltage, to produce an output which is proportional to the regulator's total output current Iout. The invention also provides a means for direct insertion of total inductor output current information into a regulator's voltage-mode control loop, to provide active voltage positioning (AVP) for the output voltage. A voltage based on total inductor output current is summed with the regulator's reference voltage; this sum and Vout are applied to the voltage control error amplifier, the output of which is processed to operate the regulator's switches. This enables the regulator's output to have a desired droop impedance and to provide AVP of Vout as a function of total filtered inductor output current Iout(fltr).

Abstract: A local oscillator apparatus is disclosed for use in radio frequency communication systems. The local oscillator apparatus comprises at least one mixer coupled to an oscillator input signal and to a feedback signal such that a local oscillator signal may be produced by fractional multiplication of the oscillator input signal. In an embodiment of the invention, the local oscillator apparatus includes a regenerative modulator comprising a pair of frequency dividers and a single side band mixer.

Abstract: The performance of a conventional op amp, having a gm stage and an integrator, is improved by placing a current mode filter between the gm stage and the integrator, which has a current gain of much less than one and is substantially without phase shift at the op amp's resonant frequency, permitting stabilization with a relatively small compensation capacitor. This improves the signal slew rate and harmonic distortion.

Abstract: A low quiescent power class AB current mirror circuit includes a first input transistor for receiving an input current and a second output transistor for providing an output current; the first and second transistors having bases connected together; and a first current supply for sinking current from the bases in response to a decrease in input current to lower the quiescent point of the transistors.

Abstract: In one embodiment, an image sensor includes a linear pixel array and array readout lines, wherein the linear pixel array includes a group of pixels arranged in a row, and each array readout line is selectively coupled to an output of at least one pixel included in the group of pixels. In another embodiment, an image sensor includes a linear pixel array and an array readout line, wherein the linear pixel array includes a first group of pixels, sensitive to a first color of light, arranged in a first row, and a second group of pixels, sensitive to a second color of light, arranged in a second row, and the array readout line is selectively coupled to outputs of pixels included in the first group of pixels and outputs of pixels included in the second group of pixels.

Abstract: A multi-channel DAC having a digital input port (2) for receiving digital input codes and a plurality of analogue output terminals (OUT1 to OUTN) on channels (CH1 to CHN) on which corresponding analogue signals are outputted, comprises a primary DAC (3) which receives the digital input codes from the input port (2). Analogue signals from the primary DAC (3) are selectively and sequentially sampled onto infinite sample and hold circuits (SH1 to SHN) of the channel (CH1 to CHN) through primary switches PS1 to PSN) under the control of a primary control circuit (5). Each infinite sample and hold circuit (SH1 to SHN) comprises a secondary DAC (10) which outputs an analogue signal which closely approximates to the sampled analogue signal from the primary DAC (3) and which is held on the corresponding output terminal (OUT1 to OUTN).

Abstract: Switched-capacitor structures are provided that reduce distortion and noise in their processed signals because they increase isolation between structural elements and ensure that selected elements are securely and quickly turned off and on in different modes.

Abstract: A multistage scrambler for a digital to analog converter having a non-ideal transfer function resulting from an error function which causes harmonic distortion includes a first shuffling network having a first input for receiving digital data and a first output, the first shuffling network including a first set of data switches; a first sequence generator for selectively interconnecting the first set of data switches to reorder at the first output the digital data received at the first input to reduce the harmonic distortion to lower magnitude colored noise; a second shuffling network having a second input for receiving the reordered digital data from the first output and a second output, the second shuffling network including a second set of data switches; and a second sequence generator for selectively interconnecting the second set of data switches to reorder at the second output the digital data received at the second input to transform the colored noise toward lower power white noise.

Abstract: Methods and apparatus are provided for spread spectrum signal processing in a wireless communication system. The apparatus includes a control processor to generate commands for processing spread spectrum signal components and a reconfigurable coprocessor to process the spread spectrum signal components based on the commands and to provide reports to the control processor based on results of processing the signal components.

Abstract: A DAC (1) comprises a pair of outer strings (4,5) of resistors Ra and Rb and an inner string (12) of resistors Rc connected in series with the outer string (4,5). The inner string (12) converts the LSBs, while the outer strings convert the MSBs. Outer switch networks (10,11) of switches Sa and Sb selectively switch the outer strings (4,5) to reference voltage terminals Vref+ and Vref− (8,9) for selectively coupling selected portions of the outer strings (4,5) to the respective voltage reference terminals (8,9) for decrementing the inner string (12) in steps corresponding to one MSB between the terminals (8,9). An inner switch network (15) of switches Sc selectively connects an analog output terminal (2) to one of the resistors Rc; corresponding to the LSBs so that the analog voltage on the output terminal corresponds to the digital input signal.

Abstract: A multi-bit sigma-delta analog to digital converter has a quantizer, a loop filter circuit, and a digital to analog feedback circuit. The quantizer, loop filter, and digital to analog feedback circuit have a loop gain associated therewith. The quantizer and loop filter have a combined gain associated therewith. The full-scale of the digital to analog feedback circuit is varied. The combined gain of the quantizer and loop filter is also varied. More specifically, the combined gain of the quantizer and loop filter is varied in inverse proportion to the full-scale of the digital to analog feedback circuit to maintain the loop gain at a substantially constant level.

Abstract: Self-calibration methods and structures are provided for pipelined ADCs which can be realized without requiring external measuring instruments or calibrators, without requiring major changes in pipeline structure and which can be rapidly obtained with stored calibration processes. In method embodiments, each of selected converter stages are calibrated by using succeeding stages as sub-ADCs which measure gain error at a transition step in a selected stage's residue transfer characteristic and saves the gain error as a calibration constant Ccal for that stage. After a first calibration constant Ccal has been obtained, the process is successively repeated for preceding converter stages except that previously-obtained calibration constants are multiplied by their respective stage's digital input signals Din to obtain weighted calibration constants Ccalwtd which are included in measured gain errors to thereby obtain preceding calibration constants Ccal.

Abstract: A high gain amplifier includes a differential amplifier stage having a pair of transistors; first and second input circuits for providing input signals to the pair of transistors; transistor means arranged as a differential-to-single-ended converter driven by the differential amplifier stage to provide a single ended output signal; an intermediate gain stage having an input responsive to the single ended output signal; bias means for the differential amplifier, the bias means including circuit means for maintaining the currents through the pair of transistors in constant ratio independently of changes in load at the intermediate gain stage; and an inverting gain output stage driven by the intermediate gain stage and having an output for driving a load substantially from rail to rail. Also disclosed is a frequency compensation capacitor circuit connected between the input of the intermediate gain stage and the output of the inverting gain output stage.

Abstract: A non-linear bulk capacitance bootstrapped current switch includes a current switch circuit including a source node and a first bulk connection having a first bulk capacitance associated with it; a current defining circuit connected to the source node and having a second bulk connection having a second bulk capacitance associated with it; and a tracking circuit for driving the voltage on at least one of the first and second bulk connections in response to the voltage on the source node to reduce the associated non-linear bulk capacitance.

Abstract: A frequency detection system for producing clock pulses having a frequency equal to the frequency of a stream of binary data. The system includes a voltage controlled oscillator for producing the clock pulses. The frequency of such clock pulses changes in accordance with a control signal. Each one of the clock pulses has four sequential, one-quarter period phases. Adjacent phases are separated by boundaries to divide each clock pulse period into four quadrants. A frequency detector is fed by detected edges of the stream of binary data and the clock pulses for producing the control signal in accordance with the difference in frequency between the frequency of the clock pulses and the frequency of the stream of binary data. A lock-out circuit prevents subsequent production of the control signal until a subsequently detected data edge crosses a different one of the boundaries.

Abstract: A rejection converter is disclosed for use in a transmitter for operating in at least either of a first mode for transmitting signals within a first frequency range, and a second mode for transmitting signals within a second frequency range. The rejection converter includes an input unit for receiving an input signal in at least either of the first or second frequency ranges. The rejection converter also includes a rejection unit for rejecting at least one spurious harmonic signal associated with the first frequency range that falls within the second frequency range. The rejection converter permits signals in the second frequency range to be passed when the output signal is within the second frequency range.

Abstract: Direct-coupled laser diode drivers are provided which eliminate the need for conventional coupling elements (e.g., capacitors and inductors) that typically introduce timing inacurracies and add complexity, size and cost to conventional drivers. The drivers are structured to reduce power dissipation and maintain sufficient transistor headroom to enhance response time and dynamic range. An exemplary driver responds to data pulses that are defined by first and second pulse levels and includes a current source that generates an imod/n current, a current mirror connected to receive the imod/n current and, in response, drive a modulation current imod through the laser diode and a differential pair of transistors that steers the imod/n current away from the modulation current mirror in response to the first pulse levels so that the modulation current mirror drives imod current pulses through the laser diode during the second pulse levels with no need for coupling elements.

Abstract: A novel array of optically and electrically interacting optical MEMS dies physically and electrically integrally attached upon an optically transmissive preferably (transparent) printed circuit substrate that is monolithically formed with one or more optical components, such as lenses, for providing fixed optical path alignment and interaction therebetween, and with provision for the integration also of active optical components such as lasers and photodiodes and the like.

Abstract: A current switching cell for a multi-cell DAC, each cell having a data input and an analog output and including a current switching circuit having a current node; a current definition circuit for providing current to the current switching circuit at the current node; the current definition circuit having a parasitic coupling between the input and the current node; a driver circuit responsive to a data input for actuating the current switching circuit to provide an analog output from the current from the current definition circuit; and a control circuit responsive to at least one common control signal for controlling the current definition circuit and isolating the parasitic coupling between the current node and the common control signal; the driver circuit may also have a parasitic coupling between its driver input and the current node and the control circuit may isolate the parasitic coupling between the current node and the driver input.