Abstract: An apparatus having a core processor and a plurality of cache memory banks is disclosed. The cache memory banks are connected to the core processor in such a way as to provide substantially simultaneous data accesses for said core processor.

Abstract: A data transmitter is having a source of data. The data is transmitted in response to clock pulses provided by a clock pulse generator. A buffer having a fixed data storage capacity is provided for storing the data transmitted by the source of data, such data being stored in response to the clock pulses. A framer is provided for retrieving the stored data in response to a data strobe signal produced by the framer and fed to the buffer. The buffer produces a control signal representative of the level of the buffer. A level signal is fed to the clock pulse generator. A superframe strobe signal samples the level of the buffer and produces a level signal representative of the sampled level of the buffer. A clock pulse generator is provided for producing the clock pulses for the data source and the buffer at a rate selected in accordance with the level of the buffer.

Abstract: A clock selection circuit for selecting one of a plurality of clocks as an output clock. When the selection circuit switches between two of the plurality of clocks for output, the currently output clock is removed from the output. The removal of the currently output clock is performed synchronously to the currently selected clock. The newly selected clock is then coupled to the output. Coupling of the newly selected clock is performed synchronously to the newly selected clock.

Abstract: An ESD protection circuit utilizes a trigger network to allow the user to select the breakdown voltage of an avalanche transistor. By implementing the trigger network as a string of diodes coupled between the collector and base of the avalanche transistor, the trigger voltage can be programmed between BVCEO and BVCBO by adjusting the number of diodes. When the voltage across the trigger network reaches a predetermined value at which the diodes are conducting under forward biased conditions, but the transistor is below BVCBO, base charge supplied to the transistor caused the transistor to avalanche. A base-emitter resistor prevents false triggering by removing leakage charge from the base of the transistor, and another resistor coupled in series with the base of the transistor limits the removal of charge, thereby causing the avalanche to be self-sustaining once initiated by the trigger network.

Abstract: An interpolator utilizes two ranks of transistors to generate a plurality of interpolator currents within the confines of a low power supply voltage. The first rank of transistors are underdriven, thereby generating a plurality of partially switched currents having shallow Gaussian-shaped functions. The partially switched currents are then spatially amplified by the second rank of transistors to reduce the overlap of the currents from adjacent transistors. The first rank of transistors are driven ratiometrically by the difference of two control currents, thereby eliminating errors caused by inaccurate resistors and current sources. A biasing op-amp senses the interpolator currents and servos the first rank of transistors, thereby regulating the interpolator currents to a value determined by a reference voltage which is temperature compensated. Thus, the biasing op-amp automatically compensates for temperature variations and manufacturing uncertainties in devices throughout the entire interpolator.

Abstract: Verniers are provided that substantially eliminate DC offset signals as they convert a differential input signal Sin to a differential output signal Sout with a conversion gain that corresponds to a digital command signal. The verniers are especially suited for use with multiplying digital-to-analog converters (MDACs) in communication systems. An exemplary use is forming line drivers to drive load impedances (e.g., coaxial cables).

Abstract: A trellis decoder identifies the closest points from each coset in a four dimensional trellis decoder by reading a received point and determining upper and lower threshold values in a signal constellation to define a decode region within the constellation. The dimensions of the decode region are based on the number of bits of information in the received signal. The decoder translates the received point in four directions to provide four image points. Any imaged point that transitions outside the constellation decode region is mapped into the decode region to ensure that the four image points are within the decode region of the constellation. For each of the cosets, bit extraction is then performed to find the closest point to the received point. Once the closest coset points are identified, the trellis decoder performs a maximum likelihood sequence estimation using the Viterbi algorithm to determine the received sequence.

Abstract: A multiplexed signal processor is described as having an input circuit for receiving multiple input signals. A modulator processes a selected input signal to produce a representative digital output. The modulator includes an integrator that integrates the difference between the selected input signal and a feedback signal representative of the digital output. A signal control circuit selects in turn by time division multiplexing each input signal for a processing period as the selected input signal, and stores the digital output and the integrator state at the end of each processing period. After an initial processing period for each input signal, each processing period begins based on the digital output and the integrator state from the end of the previous processing period for that input signal.

Abstract: A logic isolation circuit has a transmitter circuit for receiving a logic input signal and providing a periodic signal to an isolation barrier, and a receiving circuit for receiving the periodic signal from the isolation barrier and for providing an output signal that indicates the transitions in the logical input signal.

Abstract: A mixing DAC includes an analog output network; a current source; a current switching circuit connected between the current source and the analog output network; a switch driver circuit responsive to a digital input at a first rate and a clock signal having a predetermined period for driving the current switching circuit to selectively interconnect the current source and the analog output network; and a waveform generator for driving the current source to produce an output current including a plurality of peaks at a second rate during each clock period to up-convert the response energy of the DAC analog output to approximately the second rate.

Abstract: LVDS drivers and analog-to-digital (ADC) systems are provided which facilitate easy alteration (e.g., replacement of a selectable resistor Rsel) of differential current levels and differential voltages in response to altered loads. These drivers and systems maintain common-mode levels in the loads which are unaffected by alterations in the loads and their associated differential current and voltage levels.

Abstract: An active cascode amplifier circuit which includes an active cascode amplifier and an amplitude limiter. The active cascode amplifier includes an input stage, an output stage and an auxiliary amplifier and receives in a voltage input signal and outputs a voltage output signal wherein the cascode amplifier amplifies the input voltage signal. The auxiliary amplifier is provided within the circuit to increase the gain of the cascode amplifier and has an associated output. When the input stage shuts off, due to a decrease in the input voltage signal, the amplitude limiter becomes active and holds the voltage at the output of the auxiliary amplifier to a preset voltage in order to decrease the recovery time for turning the output stage on when the input voltage increases and turns the input stage on.

Abstract: An amplifier utilizes feedback compensation to extend bandwidth. A feedback network is coupled between an output stage and an intermediate stage. One or more resistors in the feedback network can be arranged to compensate for Early voltage effects in one or more transistors in the intermediate stage. One or more capacitors in the feedback network can be arranged to cancel the junction capacitance of one or more transistors in the intermediate stage.

Abstract: Direct digital synthesis (DDS) methods and structures are provided that increase DDS output frequencies fout without requiring a corresponding increase in the rate fclk at which DDS structures must operate. An exemplary method generates a periodic stream of digital words at a clock frequency fclk wherein the words represent respective amplitudes of a predetermined periodic waveform, the periodic stream has a period P and the digital words are spaced by a phase step &phgr;s.

Abstract: Current-control reference systems are provided in which stabliity is realized with sensors that shift clamp windows in response to a reference's current-control signal to thereby maintain feedback control in the reference under steady-state and transient operating conditions.

Abstract: An input distortion correction current-feedback amplifier system includes a current mirror; an input stage connected to the input of the current mirror; an output stage connected to the output of the current mirror; a feedback circuit connected from the output stage to the input stage; a compensation impedance connected to the output of the current mirror; and a distortion correction circuit for sensing the distortion voltage across the input stage and providing to the current mirror a current representative of the distortion voltage for delivering to the compensation impedance a correction current to develop a correction voltage at the input of the output stage to nullify the effect of the distortion voltage.

Abstract: A Galois field linear transformer includes a matrix responsive to a number of input bits in one or more bit streams and having a plurality of outputs providing the Galois field linear transformation of those bits; the matrix includes a plurality of cells, each cell including an exclusive OR logic circuit and AND logic circuit having an output connected to the exclusive OR logic circuit and an input connected to one of the input bits and a programmable storage device for providing an input to its associated AND logic circuit for setting the matrix to obtain a multi-cycle Galois field linear transformation of the inputs in a single cycle.

Abstract: A two-stage, pipelined modulo address generator (MAG) (30′) for generating from a current pointer into a circular buffer of size L, a next pointer into the buffer, is comprised of a pointer generation stage (32′) and a modulo correction and pointer selection stage (34′), each adapted to operate in a selected one of two modes. In the first operating mode: the pointer generation stage (32′) generates a sequential pointer which is a selected offset from the current pointer; and the modulo correction and pointer selection stage (34′) generates, modulo L, a modulo corrected sequential pointer, and provides as the next pointer the sequential pointer, if it is in the buffer, and the modulo corrected sequential pointer, otherwise.

Abstract: A calibrated current source includes current source having an output node; a calibration circuit; a load circuit; a cascode switching circuit including a pair of cascode switches, one connected between the local circuit and output node, the other connected between the calibration circuit and the output node; and a bias circuit selectively applying a bias voltage to the cascode switches to selectively connect the load circuit and the calibration circuit to the output node while maintaining a constant voltage at the output node and across the current source to provide a consistent current to the load and calibration circuits.

Abstract: A selectable input buffer control system includes at least one input buffer; a plurality of input receivers associated with each input buffer; an addresser circuit for addressing each input receiver; and a selection circuit associated with each input buffer for enabling its associated input buffer in response to the addressing of any one or more of the input receivers associated with that input buffer.