Abstract: A PLL frequency multiplier is provided having a latency substantially equal to the wake-up time of the PLL. An operative clock signal is provided to a processor while the PLL is acquiring phase lock by insuring that the clock signal does not contain frequencies above a target frequency of a PLL and below a predetermined threshold frequency. In particular, a frequency divider and a frequency detector are provided to prevent the frequency of the clock signal from operating outside the range defined by the threshold and target frequencies.

Abstract: A micromachined device has a body suspended over a substrate and movable in a plane relative to the substrate. The body has a perimeter portion, a first cross-piece portion extending from one part of the perimeter portion to another part of the perimeter portion to define at least first and second apertures, a first plurality of fingers extending along parallel axes from the perimeter portion into the first aperture, and a second plurality of fingers extending along parallel axes from the perimeter portion into the second aperture.

Abstract: A first device and a second device may be coupled to a bus. The first and second devices drive signals on the bus to establish a bus speed for a given message and to arbitrate for bus access.

Abstract: A system for encoding and decoding information of a codeblock from a memory buffer that includes a context modeler that receives from the memory buffer the codeblock and divides the codeblock into a plurality of codesegments or decodes a codeblock worth of information from received compressed data. The codesegments includes a plurality of bits. The context modeler processes each of the codesegments individually by determining whether any of the bits need special coding information or decoding. The context modeler outputs coded bits associated with the bits that are coded with the special coding information and context information associated with the coded bits or outputs a codeblock worth of information to the memory buffer. An arithmetic coder receives the context information and coded bits and compresses the coded bits or receives compressed data and decompresses the compressed data to produce context information and coded bits.

Abstract: A method for releasing a structure from contact with a substrate in a micromechanical device includes the step of irradiating the structure with energy having parameters selected to produce a thermal gradient normal to the surface of the structure which causes upward bowing and release of the structure from the substrate. Preferably, the structure is irradiated with laser energy and, more preferably, the structure is irradiated with pulsed laser energy. The temperature gradient creates a strain gradient, due to thermal expansion, which causes the structure to bow upwardly. Support elements react and hold the structure up after the thermal gradient has disappeared.

Abstract: A cover cap for semiconductor wafer devices is disclosed. According to the invention, a wafer of material that is at least one of photo-etchable or transparent is patterned and attached as a cover to a substrate including a number of semiconductor devices. Preferably, the cover wafer is made from a photo-etchable material so that portions of the cover wafer may be selectively sensitized and etched. In particular, one or more cover caps may be defined in the cover wafer such that each cover cap corresponds to a respective device on the device substrate. Once the cover wafer is attached to the device substrate to form an assembly, the assembly is diced into individual devices and the devices are packaged. The invention provides several advantages for a number of semiconductor device fabrication applications, including those relating to image sensors, and micro-machined devices such as MEMS.

Abstract: A phase inversion prevention circuit for an op amp input stage includes a detection circuit which detects when either of the input pairs' intrinsic diodes is near a forward-biased condition. When such a condition is detected, a switching network switches tail current from the primary input pair to a secondary input pair which takes over the input stage's amplifying duties. For a folded cascode input stage, the detection circuit preferably detects the onset of phase inversion by monitoring the cascode voltage which drives the cascode transistors. The outputs of the secondary input pair are connected to bypass the cascode transistors. Thus, when the onset of phase inversion is detected, the primary input pair is disabled, the second input pair is enabled, and with the cascode transistors bypassed the secondary input pair avoids phase inversion.

Abstract: A novel array of optically and electrically interacting optical MEMS dies physically and electrically integrally attached upon an optically transmissive preferably (transparent) printed circuit substrate that is monolithically formed with one or more optical components, such as lenses, for providing fixed optical path alignment and interaction therebetween, and with provision for the integration also of active optical components such as lasers and photodiodes and the like.

Abstract: Methods and apparatus are provided for sample rate conversion in a system including two or more sample rate converters. The method includes the steps of providing an input clock and an output clock to each of the sample rate converters, measuring a sample rate ratio of the clocks in one of the sample rate converters, designated as a master, and controlling each of the sample rate converters with the sample rate ratio measured by the master. The measured sample rate ratio may be transmitted from the master to each of the other sample rate converters. This approach matches the group delays among the sample rate converters.

Abstract: An accelerometer has a movable electrode between two fixed electrodes to form a differential capacitor. Drivers provide AC drive signals to the fixed electrodes. The movable electrode is coupled through reading circuitry to an output terminal. In response to a sensed acceleration, feedback is provided from the output terminal to one or both drivers to null any AC signal on the movable electrode and to keep the electrostatic forces between the movable electrode and each of the fixed electrodes equal.

Abstract: An electronic meter includes a sensing circuit for sensing voltage and current values of a waveform, an analog-to-digital converter for converting the sensed voltage and current values to digital voltage and current values, a digital filter for delaying one or both of the digital voltage and current values to compensate for a phase shift error in the sensing circuit, and a computation circuit for computing one or more parameters of the waveform in response to the phase compensated voltage and current values. The electronic meter may be calibrated by applying to the meter a test waveform having a known phase shift, measuring the phase shift using the electronic meter, determining a phase shift error based on the difference between the known phase shift and the measured phase shift and determining digital filter coefficients to produce a digital filter delay that corresponds to the phase shift error.

Abstract: A data processor is provided which has integrated therein at least two of a bootstrap memory, a program memory and a data memory, wherein the at least two memories are of the same construction. In an exemplary embodiment, the memories are flash EEPROM memories. The data memory is provided with registers for temporarily storing the contents of an entire row of memory such that modifications can be easily made to a single bit within the row by storing the contents of the row, erasing the row, modifying the data and storing the data back in the row.

Abstract: An operating circuit (1) for controlling the speed of a cooling fan motor (3) for computer cabinetry (7), and for determining an under-speed condition in the fan motor (3) comprises a control circuit (15) which controls a variable output signal generator circuit (18) for outputting a pulse width modulated signal corresponding to the desired fan speed for switching a switching circuit (8) in a power supply circuit of the fan motor (3) for pulse width modulating the power supply to the fan motor (3). A monitoring resistor (R1), a capacitor (C1) and a circuit (12) provides a tachometer signal to the operating circuit (1). A gate circuit (22) gates the second and fourth pulses of the tachometer signal to a counter (20) which counts clock pulses from a clock signal generating circuit (19) between the rising edges of the second and fourth pulses which are in turn stored in a register (23) for comparison with a reference count by a comparator (25).

Abstract: Transimpedance amplifiers are provided that generate low-distortion output voltage signals with simple, inexpensive structures that are compatible with integrated-circuit fabrication processes. The amplifiers include a current processor and a complementary output stage. The processor provides in-phase upper and lower current signals in response to a differential input current signal and differentially alters respective first and second amplitudes of these signals in response to a common-mode input current signal. The complementary output stage has upper and lower transistors that provide the output voltage signal in respective response to the upper and lower current signals and with distortion that is reduced by the altered first and second amplitudes.

Abstract: A variable gain amplifier system for radio frequency signals is disclosed. The system provides a relatively constant gain change in decibels responsive to an incremental change in control voltage. The system includes two or more cascaded gain stage amplifiers. Each gain stage amplifier is adjustable between a first gain setting and a second gain setting.

Abstract: A logic isolation circuit has a transmitter circuit for receiving a logic input signal and providing a periodic signal to an isolation barrier, and a receiving circuit for receiving the periodic signal from the isolation barrier and for providing an output signal that indicates the transitions in the logical input signal.

Abstract: A method for developing an integrated circuit chip design includes the steps of developing an architecture specification defining the functions of the chip, developing a microarchitecture specification based on the architecture specification, developing a functional and structural model of the chip based on the microarchitecture specification, designing software tools for use with the chip based on the architecture specification, and designing chip verification tools based on the microarchitecture specification. The activities associated with chip development are divided into phases which may be performed concurrently. The result of the development is an RTL model of the chip which can be utilized in implementation of products without comprising proprietary circuit, layout and fabrication process information of the entity that is implementing the products.

Abstract: An input system for a variable gain amplifier using a continuously interpolated attenuator includes a plurality of gm stages in which the collector current from one transistor in each gm stage is diverted to AC ground, thereby eliminating a feedforward path and providing flat frequency response at very high frequencies. An additional feedforward path through the parasitic emitter capacitances in each gm stage is eliminated by a filter capacitor coupled the common emitter node of each gm stage. A compensation transistor included in each gm stage provides a differential output signal which can be used to cancel common mode feedforward signals which are coupled to the output through the collector-junction capacitances of the gm stages. The effects of parasitic capacitances are further reduced by reverse biasing the gm stages that are off.

Abstract: Feedback methods and systems are provided to achieve rapid switching of oscillator frequencies without compromising operational feedback loop bandwidths that filter out spurious tones and phase noise to thereby enhance loop spectral and noise performance. The methods respond to frequency changes in a reference signal by providing an open-loop drive current to drive a feedback signal towards the reference signal. The drive current is terminated and the feedback control loop closed when the feedback signal is within a predetermined acquisition range of the reference signal. This is determined by successively comparing a feedback frequency of the feedback signal to a destination frequency of the reference signal over a comparison window of time. The invention also provides a feedback control system that practices the invention's methods.

Abstract: An RMS-DC converter generates a series of progressively amplified signal pairs which are then multiplied and weighted in such a way as to cancel uncorrelated noise while still providing true square-law response. The converter includes two series of gain stages for generating the amplified signal pairs, and a series of four-quadrant multipliers for multiplying and weighting the amplified signal pairs in response to a series of weighting signals. The outputs from the multipliers are summed and averaged, and a final output signal is generated by integrating the difference between the averaged signal and a reference signal. To preserve the square-law response over a wide range of input voltages, the system is servoed by feeding the final output signal back to an interpolator which generates the weighting signals as a series of continuously interpolated, overlapping, Gaussian-shaped current pulses having a centroid that moves along the length of the interpolator as the final output signal varies.