Abstract: A method for testing a Coriolis transducer having a mass adapted vibrate along a vibratory direction in a resonant structure and undergo a displacement along a sensitive axis, perpendicular to the vibration, in response to an angular rate about a mutually perpendicular rate sensing axis. In the absence of an angular rate about the rate sensing axis, forces, FTEST VIBRATORY and FTEST SENSITIVE are applied on the mass along the direction of vibration and along the sensitive axis, respectively, in a predetermined ratio, N. The output VOUT TEST of the transducer is measured in response to the forces, FTEST VIBRATORY and FTEST SENSITIVE.

Abstract: A bipolar rail-to-rail input stage includes complementary differential input pairs, and a switching circuit which makes one or the other of the input pairs active depending on the relationship between a transition threshold voltage Vth and the common mode input voltage Vcm. A transition threshold voltage selection circuit provides a selectable one of at least two different Vth voltages to the switching circuit in response to a select signal. In one embodiment, the select signal has logic “high”, logic “low”, and “floating” states. The transition threshold voltage selection circuit provides a first Vth voltage when the select signal is in a first state, a second Vth voltage when the select signal is in a second state, and disables the input stage when the select signal is in a third state.

Abstract: An amplifier circuit includes a first operational amplifier having an inverting input and a non-inverting input. The non-inverting input receives an input signal, and the inverting input is connected to a noise generating system. The amplifier circuit further includes a second operational amplifier having an inverting input and a non-inverting input. The non-inverting input of the second operational amplifier receives an input signal, and the inverting input is connected to a noise generating system. A differential in/out operational amplifier, in the amplifier circuit, has an inverting input connected to an output of the second operational amplifier and a non-inverting input connected to an output of the first operational amplifier. The noise generating system injects a narrow band noise into a differential amplifier with no insertion loss and mismatching along the signal path. The narrow band noise is obtained by amplifying thermal noise of an amplifier. The amplified thermal noise is bandwidth limited.

Abstract: A multi-phase, multi-access pipeline memory system includes a number, n, of processors; a pipeline memory including a latch; and a bus for interconnecting the processors and pipeline memory; a clock circuit responsive to a system clock signal divides the system clock signal into n phases for providing multiple clock signals corresponding to the n phases of the system clock signal for application to each processor to allow data and address to be transferred only during its assigned phase thereby enabling the memory and each processor to operate at the system clock rate while allowing n accesses to the memory during each system clock signal period, one access for each processor.

Abstract: A method for testing a Coriolis transducer having a mass adapted vibrate along a vibratory direction in a resonant structure and undergo a displacement along a sensitive axis, perpendicular to the vibration, in response to an angular rate about a mutually perpendicular rate sensing axis. In the absence of an angular rate about the rate sensing axis, forces, FTEST VIBRATORY and FTEST SENSITIVE, are applied on the mass along the direction of vibration and along the sensitive axis, respectively, in a predetermined ratio, N. The output VOUT TEST of the transducer is measured in response to the forces, FTEST VIBRATORY and FTEST SENSITIVE.

Abstract: In one embodiment, an image sensor includes an area pixel array, column readout lines, and array readout lines, wherein the area pixel array includes columns of pixels, each including pixels of a first type, each column readout line is selectively coupled to outputs of the pixels of the first type that are included in a respective column of pixels, and each array readout line is selectively coupled to at least one of the first column readout lines. In another embodiment, an image sensor includes a pixel array, column readout lines, and array readout lines, wherein the pixel array includes a row of pixels which includes pixels of a first type, each column readout line is selectively coupled to an output of a respective pixel of the first type that is included in the row of pixels, and each array readout line is selectively coupled to at least one of the column readout lines.

Abstract: Optical mirror coatings are used for high-temperature diffusion barriers and mirror shaping. Certain materials for use as high-temperature diffusion barriers under optical mirror coatings include metals that have high melting and/or boiling points and amorphous and partially recrystallized inorganic amorphous materials that have high glass transition temperatures (Tg). Candidate metals are selected based upon the boiling point or a combination of melting point and boiling point. Candidate amorphous and partially recrystallized inorganic amorphous materials are selected based upon the glass transition temperature. Optical mirrors having such high-temperature diffusion barriers maintain reflectivity when exposed to elevated temperatures, and are particularly useful in optical Micro Electro-Mechanical Systems (MEMS) that are exposed to high-temperature manufacturing processes. Optical mirrors are shaped using tensile and/or compressive films.

Abstract: A computation block for use in a digital signal processor includes a register file for storage of operands and results and one or more computation units for executing digital signal computations. A first digital signal computation is performed with one of the computation units, and an intermediate result is produced. The intermediate result is transferred from a result output of the computation unit to an intermediate result input of one or more of the computation units without first transferring the intermediate result to the register file. A second digital signal computation is performed using the intermediate result to produce a final result or a second intermediate result.

Abstract: A circuit is presented which sets the transconductance of a FET using a resistor. The circuit comprises a resistor and first and second FETs series-connected in sequence between a supply voltage and a circuit common point, and third and fourth FETs and a bias current source series-connected in sequence between the supply voltage and the circuit common point. The drain and gate of the fourth FET are connected to the gate of the second FET and the gates of the first and third FETs are cross-coupled to the drains of the third and first FETs, respectively. The bias current source provides a starting current for the circuit. When so arranged, and with the threshold voltages of the first and second FETs matched, the transconductance of the second FET is directly proportional to 1/R1. The circuit can in turn be used to bias other transistors in a reproducible way to fix the transconductance of an amplifier according to the selected resistor value.

Abstract: A clamp for use with a circuit (having an output for delivering an output voltage) forms a voltage boundary for the output voltage based upon a clamp voltage. To that end, the clamp includes a clamp input for receiving the clamp voltage, a clamp transistor in communication with the clamp input, and a control transistor in communication with the output. The clamp also includes a driving source for driving at least one of the clamp and control transistors based upon the voltage at the clamp input and the voltage at the output. The output is clamped at a voltage within the voltage boundary of the clamp voltage after the clamp transistor begins being driven by the driving source.

Abstract: A micromachined gyroscope has first and second coplanar bodies suspended over a substrate and movable in their plane relative to the substrate. The first body is dithered along a dither axis and is movable relative to the second body on the dither axis, but is rigidly connected for movement along an axis transverse to the dither axis. The second body is anchored so that it is substantially inhibited from moving along the dither axis, but can move with the first body along the transverse axis. The gyro has stop members and an anti-levitation system for preventing failure.

Abstract: A micromachined gyroscope has first and second coplanar bodies suspended over a substrate and movable in their plane relative to the substrate. The first body is dithered along a dither axis and is movable relative to the second body on the dither axis, but is rigidly connected for movement along an axis transverse to the dither axis. The second body is anchored so that it is substantially inhibited from moving along the dither axis, but can move with the first body along the transverse axis. The gyro has stop members and an anti-levitation system for preventing failure.

Abstract: A method for reducing DC offset from a receiver signal. The method includes jointly (i.e., simultaneously) estimating such DC offset and channel impulse response, and reducing the DC offset in accordance with the estimated DC offset and the estimate of the channel impulse response.

Abstract: A digital radio tuner signal estimator receives a digitized in-phase (I) data signal and a digitized quadrature (Q) data signal and provides an estimated amplitude gain signal and an estimated signal-to-noise ratio signal value. The signal estimator includes a symmetrical matched I data digital filter having a first I filter section that filters the received I data signal and provides a first I data signal, and a second I filter section that filters the I data signal and provides a second I data signal. The signal estimator also includes a symmetrical matched Q data digital filter having a first Q filter section that filters the received Q data signal and provides a first Q data signal, and a second Q filter section that filters the Q data signal and provides a second Q data signal. The first and second I data signals and the first and second Q data signals are processed to compute an estimated amplitude gain.

Abstract: An input bias current reduction circuit for multiple input stages having a common input includes a plurality of input stages each including a first input transistor with its base connected to the common input and the first current sensing transistor with its collector-emitter in series with the collector-emitter of the first input transistor and its base current replicating that of the first transistor; and a current compensation circuit for sensing the base current of the first current sensing transistor in each input stage and subtracting that from the base current of the first input transistor in each input stage for maintaining constant reduced current loading of the input.

Abstract: A voltage source circuit adapted to provide a regulated output voltage independent of variations in an input voltage and having an input node adapted to receive an input reference current and an output node adapted to provide a definable voltage output. The circuit comprises a control element adapted to provide an output signal to the output node, an impedance being driven by the output signal of the control element, and a sensing element having a current mirror adapted to sense the current flowing through the impedance, and to provide a feedback signal. The control element is responsive to the difference between the feedback signal and the input reference current, thereby providing a regulated voltage output.

Abstract: A circuit used for testing an integrated circuit including a chop circuit. A source of a test signal coupled to a first pair of pins of the integrated circuit. A test signal measuring device to measure the test signal coupled to a second pair of pins of the integrated circuit. A chop circuit controller produces a control signal and for feeding such control to the chop circuit and the test signal measuring device. In response to the control signal, the chop circuit couples the first pair of pins to the second pair of pins with a first polarity during a first period of time and couples the first pair of pins to the second pair of pins with an opposite polarity during a second period of time.

Abstract: A ping-pong amplifier includes two differential amplifiers A1 and A2 and an error amplifier. The error amplifier has one input connected to a predetermined common-mode reference voltage VCMR, its other input switchably connected to the common-mode outputs of A1 or A2, and an output which is switchably connected to the common-mode reference (CMR) voltage inputs of A1 and A2. Respective memory capacitors CM1 and CM2 are connected to the two CMR inputs. The error amplifier is periodically connected between A1's common-mode output and its CMR input to form a closed-loop which forces A1's common-mode output voltage to be equal to VCMR, with the error amplifier's output voltage stored on CM1. A2's common-mode output voltage is similarly calibrated, with the error amplifier's output voltage stored on CM2. Both common-mode output voltages are thus made equal to VCMR, thereby reducing transients that might otherwise appear in the output as the amplifier ping-pongs between A1 and A2.

Abstract: A circuit comprises a current source providing an input current, first and second transistors having common control terminals and forming a current mirror connected between first and second power supply potentials, with the first transistor having an input coupled to the current source, the current mirror generating a mirror current at an output of the second transistor, and an amplifier connected in a negative feedback loop around the first transistor, wherein the amplifier input is referenced to the first power supply potential, and the amplifier output is referenced to the second power supply potential. A method for improving power supply rejection ratio of a current mirror is also described.

Abstract: A direct digital waveform synthesiser with DAC error correction includes a digital to analog converter system for producing a desired output waveform and having between its digital and analog output a characteristic having a linear component and a non-linear component; and a phase to amplitude converter including a storage device responsive to phase inputs to provide to the digital to analog converter system amplitudes modified to compensate for the non-linear component of a characteristic of the digital to analog converter system.