Abstract: Amplifier systems and methods are provided which closely approximate a constant output impedance and a constant quiescent output signal during forward and reverse modes of operation. The systems can be realized with small, inexpensive components that are compatible with integrated-circuit fabrication processes. A system embodiment includes a signal amplifier, a feedback path that is coupled across at least part of the signal amplifier to reduce its impedance, a reverse amplifier which is coupled to drive at least a feedback portion of the feedback path and a signal generator which controls operational timing of the signal amplifier and reverse amplifier. Another system embodiment includes an error-current canceler that cancels error currents of the signal amplifier with substantially equal and opposite correction currents.

Abstract: A four current transistor temperature sensor comprises a p-n junction, preferably the base-emitter junction of a bipolar transistor, which is driven with four different currents in a predetermined sequence. Each of the four currents induces a respective base-emitter voltage, which is measured. The temperature of the transistor is calculated based on the values of the four driving currents and the four measured base-emitter voltages. The four driving currents (I1, I2, I3 and I4) are preferably arranged such that I1=2*I3, I2=2*I4, I1/I2=A and I3/I4=A, where A is a predetermined current ratio. I1 and I2 produce respective base-emitter voltages which are subtracted from each other to produce &Dgr;Vbe1, and I3 and I4 produce respective base-emitter voltages which are subtracted from each other to produce &Dgr;Vbe2. When so arranged, the difference between &Dgr;Vbe1 and &Dgr;Vbe2 is entirely due to the effect of series base and emitter resistances rb and re.

Abstract: A fractional-N synthesizer and method of phase synchronizing the output signal with the input reference signal in a fractional-N synthesizer by generating a synchronization pulse at integer multiples of periods of the input reference signal and gating the synchronization pulse to re-initialize the interpolator in the fractional-N synthesizer to synchronize the phase of the output signal with the input reference signal.

Abstract: Latch structures and systems are disclosed that enhance latch speed and reduce latch current drain while providing complementary metal-oxide-semiconductor (CMOS)-level latch signals. They are realized with bipolar junction structures and CMOS structures that are arranged to limit latch currents in response to CMOS-level sense signals Ssns.

Abstract: A packaged device includes a package substrate and a plurality of optical structures formed on a semiconductive substrate and positioned on the package substrate, forming an active area. The packaged device further includes a contiguous solderable seal structure surrounding the plurality of optical structures and a cap formed over the plurality of optical structures and upon the contiguous solderable seal structure. The cap has, formed thereon, patterned metalization. The patterned metalization is located over the active area.

Abstract: A wafer cap protects micro electromechanical system (“MEMS”) structures during a dicing of a MEMS wafer to produce individual MEMS dies. A MEMS wafer is prepared having a plurality of MEMS structure sites thereon. Upon the MEMS wafer, the wafer cap is mounted to produce a laminated MEMS wafer. The wafer cap is recessed in areas corresponding to locations of the MEMS structure sites on the MEMS wafer. The capped MEMS wafer can be diced into a plurality of MEMS dies without causing damage to or contaminating the MEMS die.

Abstract: A wireless terminal circuit includes a variable high frequency clock oscillator that provides a high frequency clock signal and a fixed low frequency clock oscillator that provides a low frequency clock signal. A phase-locked loop adjusts a ratio of the frequency of the high frequency clock signal to the low frequency clock signal by adjusting the frequency of the high frequency clock signal. The phase locked loop includes a divider for dividing the high frequency clock signal, the divide ratio of which divider is controlled by a sigma-delta modulator. A wireless terminal local oscillator calibration circuit includes a frequency control circuit including both the high frequency clock oscillator and the low frequency clock oscillator.

Abstract: A logic buffer includes a logic gate having at least two input terminals and two output nodes, a plurality of output terminals, each having a capacitance associated therewith and a pull-up circuit interconnected between each output node and the plurality of output terminals for alternately charging the capacitance of each output terminal. The buffer also includes a differential pull-down circuit including a common pull-down current source, the pull-down device interconnected between the output nodes and the output terminals for inversely alternately discharging the capacitances through the common pull-down current source for accelerating the discharge of the capacitance of the respective output terminal.

Abstract: Electro-mechanical structures and methods for forming same are disclosed. The structures are integratable onto an integrated circuit. The structures have a deformeable element formed in a plane substantially perpendicular to the substrate of the integrated circuit.

Abstract: A dynamic power controller is provided that identifies a clock frequency requirement of a processor and determines a voltage requirement to support the clock frequency requirement. The dynamic power controller transitions the processor to a power state defined by the clock frequency requirement and the voltage requirement. In particular, a voltage level indicated by the voltage requirement is supplied to the processor and the frequency distribution indicated by the frequency requirement is provided to the clocks signals of the processor.

Abstract: A high gain amplifier includes an intermediate gain stage; an output gain stage driven by the intermediate gain stage; an input stage, for driving the intermediate gain stage, which is balanced between positive and negative feedback in normal operation; bias means for driving the input stage to maintain balance between positive and negative feedback in normal operation; and a resistance for limiting the output current of the intermediate stage in response to the input stage being overdriven into positive feedback.

Abstract: An RMS-to-DC converter implements the difference-of-squares function by utilizing two identical squaring cells operating in opposition to generate two signals. An error amplifier nulls the difference between the signals. When used in a measurement mode, one of the squaring cells receives the signal to be measured, and the output of the error amplifier, which provides a measure of the RMS value of the input signal, is connected to the input of the second squaring cell, thereby closing the feedback loop around the second squaring cell. When used in a control mode, a set-point signal is applied to the second squaring cell, and the output of the error amplifier is used to control a variable-gain device such as a power amplifier which provides the input to the first squaring cell, thereby closing the feedback loop around the first squaring cell.

Abstract: An adjustable offset voltage circuit is disclosed for applying an offset voltage to a differential voltage in a digital data receiver system. The circuit includes a pair of emitter follower units, and a pair of current generating units. The first emitter follower unit provides a first offset voltage, and the second emitter follower unit provides a second offset voltage. The first current generating unit provides a biasing current to the first emitter follower unit, and the second current generating unit provides a biasing current to the second emitter follower unit. The circuit also includes a pair of differential signal input ports, each of which is coupled to one of the first and second emitter follower units, and an offset adjustment unit for permitting offset adjustment of a differential output signal with respect to a differential input signal at the input ports.

Abstract: Feedback control loop systems are provided that enhance output-signal switching times without degrading other loop performance parameters. The systems reduce “kick-back” voltages that are generated in a loop filter by drive currents which rapidly drive a control loop oscillator to a loop acquisition range. This reduction reduces a frequency step in the oscillator output signal which would otherwise have to be driven to eliminate the frequency step with a consequent increase in the output-signal switching time. Structures are provided that reduce the kick-back voltage to thereby enhance output-signal switching times.

Abstract: A differential variable gain amplifier (VGA) with constant input impedance and an adjustable one-pole filtering characteristic is provided. Each input of the VGA has a set of parallel resistors connected thereto. Except for one resistor in each set, each of the resistors of the two sets is connected to its corresponding summing junction (op-amp input), or to a corresponding resistor of the other set via a switch. Switching the resistors to their corresponding summing junction or to the corresponding resistor of the other set provides for the variable gain function, where the gain is proportional to the number of resistors connected to the summing junction. The configuration of resistors provides a constant input impedance to the VGA of R/(n+1), where R is the resistance value of the resistors.

Abstract: An adaptive equalizer provides different degrees of high frequency boosts to the received signal, while retaining a relatively constant phase shift for each boost setting. The response of the equalizer is controlled by a control circuit (e.g., a digital signal processor) to compensate for the high frequency signal attenuation primarily caused by the signal path. For example, the signal path may include a telephone line between the communications system (e.g., a modem) and the central office. The dynamic response of the equalizer is selected based upon the characteristics of the signal path which the receive signal travels along. The equalizer may receive single ended or doubled ended signals. Advantageously, the equalizer conditions the received signal to ensure efficient utilization of the dynamic range of the ADC located in the receive circuit path. The equalizer is suitable for on-chip implementation, resulting in lower cost and power consumption.

Abstract: A method of equalizing total signal delay across a digital to analog interface includes constructing a plurality of unit digital to analog converter cells each having a clock input and a data input and an analog output; constructing an analog output network for summing the analog outputs for delivery to a termination which in combination with the analog output network defines a first predetermined time delay between the unit cells; constructing a clock input distribution network for propagating a clock input to each of the unit cells tapped along the clock input distribution network; and connecting a second termination to the clock input distribution network for establishing the clock input distribution network as a transmission line and defining in combination with the clock input distribution network a second predetermined time interval delay between the clock input to the unit cells equal to the first predetermined in the interval delay for synchronizing the propagation of the clock inputs propagating alon

Abstract: A crystal oscillator circuit is disclosed including a differential amplifier, a positive feedback assembly, and a series resonant crystal assembly. The differential amplifier includes a first transistor and a second transistor. The positive feedback assembly is coupled to each of the first and second transistors, and has a loop gain of greater than unity. The series resonant crystal assembly is coupled to one of the first and second transistors, and includes a crystal and a capacitor.

Abstract: A method, apparatus and product for use in generating a remainder based code generates a plurality of preliminary remainder based codes in response to specified data, and synthesizing a remainder based code for the specified data, in response to the plurality of preliminary remainder based codes. In one embodiment, the plurality of preliminary remainder based codes includes at least two preliminary remainder based codes each generated in response to a respective portion of the specified data. In another embodiment, at least two preliminary remainder based codes are generated at least partially concurrently with one another.

Abstract: A voltage mode digital-to-analog converter (DAC) with an output buffer operational amplifier is provided with a rail-to-rail output voltage capability by reducing the DAC's output voltage swing to a range that is within the amplifier's permissible input signal range, and connecting the amplifier in a multiplier configuration to produce a corresponding multiplication of its input signal. The DAC output reduction is preferably achieved by delivering an n-bit input digital signal to an n+m bit DAC, and holding the DAC's m most significant bits OFF. The m most significant bits are dummy bits that are impedance matched with the DAC, while the amplifier is an operational amplifier with a feedback circuit that is also impedance matched to the DAC.