Abstract: A tunable, active RC filter and method of tuning the active RC filter which prevents distortions introduced during tuning. Generally, each tuning element in the feedback loop of the tunable active RC filter comprises a capacitor, a first switch, a second switch, and a third switch. The first switch connects a first terminal of the capacitor to a summing junction at the input of the op-amp when closed. When closed, a second switch connects the first terminal of the capacitor to a replica of the voltage present at the summing junction (input) of the op-amp to which the first terminal of the reactance element is connectable via the first switch. A third switch, when closed, connects the first terminal of the capacitor to the second terminal of the reactance element, which is connected the output of the op-amp.

Abstract: A data communication network operating in asynchronous transfer mode has a data transmission node and a data reception node. The nodes transfer data cells having associated headers followed by associated payloads. Each header indicates whether or not the associated cell is unassigned, is idle, or has an erroneous header. A filter of the data reception node stores each header of the sequentially received cells in a header memory. The filter stores, in a cell memory, cells that are non-idle, are assigned, and have non-erroneous headers. The filter rejects from storage payloads associated with idle, unassigned, and erroneous cells.

Abstract: Individual caps are provided for mutually spaced MEMS on a common wafer by establishing a fixed spatial array of caps in positions that correspond to the positions of the MEMS on the wafer, and simultaneously bonding the caps to corresponding MEMS. The caps are preferably held in place within recesses in a template, and include protective sealing rings that are bonded to the MEMS wafer. The wafer is diced into individual MEMS chips after the caps have been bonded. The caps can be provided with circuitry that faces away from MEMS wafer and is wire bonded to the wafer, or that faces towards the wafer with a flip-chip mounting.

Abstract: A low noise amplifier in accordance with the present invention provides extended dynamic range by sequentially interpolating an array of commonly connected gain stages. The gain stage at one end of the array has a small input signal range, but very low noise. Moving along the array, the gain stages have progressively wider input signal range, but higher noise. By sequentially enabling and disabling the gain stages with an interpolator, the amplifier can provide very low noise operation, while still accommodating larger signals when necessary. Continuous interpolation techniques are preferably utilized to provide smooth transitions between stages. The outputs from the gain stages are coupled to a loading network which is preferably weighted such that the overall gain remains constant regardless of which gain stage is enabled. A buffer amplifier and shunt feedback network provide active impedance matching.

Abstract: An apparatus having a core processor and a memory system is disclosed. The core processor includes at least one data port. The memory system is connected in such a way as to provide substantially simultaneous data accesses through the data port. The memory system can be made user configurable to provide appropriate memory model.

Abstract: A method of fabricating MicroElectroMechanical systems. The method includes: providing a substrate in which electrical interconnections and a sacrificial layer have been formed, forming a release mask including germanium, etching exposed sacrificial material, and removing the release mask. The performance of MicroElectroMechanical devices is improved by 1) integrating electronics on the same substrate as the mechanical elements, 2) increasing the proximity of electronics and mechanical elements, 3) increasing the undercut of a release etch to reduce or eliminate etch holes or to allow circuit elements to be undercut, 4) increasing the yield and reliability of the MEMS release processes. In addition to released mechanical structures, the invention also provides a means for forming circuits such as a bandgap reference as a released MEMS element.

Abstract: A hermetically sealed wafer scale package for micro-electrical-mechanical systems devices. The package consists of a substrate wafer which contains a microstructure and a cap wafer which contains other circuitry and electrical connectors to connect to external applications. The wafers are bonded together, and the microstructure sealed, with a sealant, which in the preferred embodiment is frit glass. The wafers are electrically connected by a wire bond, which is protected by an overmold. Electrical connectors are applied to the cap wafer, which are electrically linked to the outputs and inputs of the microstructure. The final package is small, easy to manufacture and test, and more cost efficient than current hermetically sealed microstructure packages.

Abstract: A method and apparatus for reducing offset errors in a variable gain circuit is offered. A first programmable gain amplifier is located in a feedforward signal path and a second programmable amplifier is connected in feedback with the first programmable gain amplifier. Each programmable gain amplifier has a separate gain control circuit so that the gain of each programmable gain amplifier can be independently controlled.

Abstract: A CCD signal processing channel with input and output offset correction is offered. Integrators are positioned to provide correction at the input to a correlated double sampling circuit and at the output of a programmable gain amplifier. Gain control is provided for the programmable gain amplifier. The second integrator may be all digital or may combine analog and digital signals. The channel may also be constructed using a digital programmable gain amplifier. The digital programmable gain amplifier can be combined with an analog programmable gain amplifier in the signal processing channel.

Abstract: An RMS-DC converter generates a series of progressively amplified signal pairs which are then multiplied and weighted in such a way as to cancel uncorrelated noise while still providing true square-law response. The converter includes two series of gain stages for generating the amplified signal pairs, and a series of four-quadrant multipliers for multiplying and weighting the amplified signal pairs in response to a series of weighting signals. The outputs from the multipliers are summed and averaged, and a final output signal is generated by integrating the difference between the averaged signal and a reference signal. To preserve the square-law response over a wide range of input voltages, the system is servoed by feeding the final output signal back to an interpolator which generates the weighting signals as a series of continuously interpolated, overlapping, Gaussian-shaped current pulses having a centroid that moves along the length of the interpolator as the final output signal varies.

Abstract: A switched capacitor correlated double sampling circuit includes an op amp, an input sampling capacitor, and a feedback capacitor. The input capacitor samples the input signal during a first time phase and the feedback capacitor receives the signal charge from the input capacitor. No sampling switch is located between the input capacitor and the input terminal.

Abstract: A microstructure and method for forming the microstructure are disclosed. The method includes: providing a handle substrate; providing a device substrate in which high-aspect-ratio structures and optional integrated circuitry will be fabricated; forming one or more filled isolation trenches within a recessed cavity on a first surface of the device substrate or alternatively forming one or more filled isolation trenches on a first surface of the device substrate and forming a recessed cavity on a first surface of the handle substrate; bonding the first surface of the device substrate to the first surface of the handle substrate; removing a substantially uniform amount of material from the second surface of the device substrate to expose at least one isolation trench; optionally forming circuits and interconnection on a second surface of the device substrate; and etching a set of features in the second surface of the device substrate to complete the definition of electrically isolated structural elements.

Abstract: An electronic power meter for metering the consumption of electrical energy on power lines includes phase compensation on current transformers, whereby the acquisition of one of the two samples for the current signals is delayed and time shifted averaged, such that the average of the two signals provides a compensated signal. The amount of delay is determined from the phase lag the current transformers exhibit during the process of calibration for phase compensation. The amount of compensation that is applied varies with current, thus compensation for the non-linearity in the phase shift for the current transformers. The degree of non-linearity is computed which results in only two variables that define the phase lag at higher current and the degree of non-linearity. The technique helps in using inexpensive current transformers in the meter.

Abstract: An RMS-DC converter provides extended dynamic range by driving a squaring cell with a variable gain amplifier. Temperature effects in the squaring cell can be cancelled by driving a second squaring cell with a reference signal and averaging the difference between the output signals from the two squaring cells. In a transmission system utilizing a power measurement system having two detector cells, square-law conformance errors in the detector cells can be cancelled by driving one of the detectors cells with a replica of the baseband modulation signal.

Abstract: A multi-stage, low-offset, fast-recovery, comparator system and method for: reducing the input offset voltage of the zeroing amplifier by a factor essentially equal to gain of the zeroing amplifier; reducing the input offset voltage of the combined main and zeroing amplifiers by a factor essentially equal to the product of the gains of the main and zeroing amplifiers; and amplifying the input signal to the amplification stage in accordance with the gain of the main amplifier to generate an amplified high-resolution signal.

Abstract: A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through. the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.

Abstract: A digital blanking circuit allows a first digital input signal transition to be passed on to a following stage, but prohibits the passing of subsequent transitions for a predetermined blanking interval. One embodiment of the present invention employs rising edge and falling edge latches, the inputs of which receive the digital input signal and the outputs of which are connected to a two-to-one multiplexer. The mux output is connected to a blanking interval circuit, which is triggered to begin timing a blanking interval by a multiplexer output transition. The blanking interval circuit provides outputs which control the latches and selects the latch output to be transferred to the multiplexer output such that the multiplexer output is prevented from transitioning during a blanking interval.

Abstract: In one embodiment, a pipelined processor is described that includes an execution pipeline having a plurality of stages and a multi-cycle instruction (MCI) controller adapted to assert a stall signal to stall the multi-cycle instruction within one of the stages of the execution pipeline. The MCI controller is adapted to issue a plurality of instructions to subsequent stages in the pipeline while the multi-cycle instruction is stalled.

Abstract: A thin film resistor fabrication method requires that an IC's active devices be fabricated on a substrate, and a dielectric layer be deposited over the devices to protect them from subsequent process steps. A layer of thin film material is deposited next, followed by a barrier layer and a first layer of metal. These three layers are patterned and etched to form isolated material stacks wherever a TFR is to be located, and a first level of metal interconnections. The first metal layer is removed from the TFR stacks, and the barrier layer is patterned and etched to provide respective openings which define the active areas of each TFR. In a preferred embodiment, a dielectric layer is deposited after the first metal layer is removed, to protect the interconnect metal from corrosion and as an adhesion layer for the patterning of the openings which define resistor length.

Abstract: Resolver systems are described that generate an estimate &phgr; of a rotatable member's position angle &thgr; and provide fault signals which monitor the reliability and accuracy of the estimate. The fault signals are formed from a monitor signal which multiplies resolver and estimate signals to derive information on the absolute and relative levels of resolver sense signals. At least one fault signal is formed from a loop error signal of the system servo loop. The fault signals report on, for example, mismatched sense signals, out-of-range sense signals and loss of position tracking to thereby enhance accuracy and safety in various resolver applications.