Abstract: In a voltage-switching digital-to-analog converter, each bit is switched by a switching circuit which uses a p-channel MOSFET as a V.sub.ref switch and an n-channel MOSFET as an Agnd switch, with a control circuit for controlling the signal applied to the gate of one of the devices (e.g., the n-channel device) to cause its "ON" resistance to match the "ON" resistance of the other device (e.g., the p-channel device). The control circuit includes reference n-channel and p-channel devices. A control signal is developed to drive the reference n-channel device to a condition wherein its drain current and drain-source voltage match those of the reference p-channel device, thereby causing their R.sub.ON s to match. The drive signal is taken as the output of the control means and is used to power the driver for the n-channel Agnd switches.

Abstract: A monolithic chip with an integrated circuit forming an 18-bit D/A converter powered by a single supply of +5 volts. The circuit includes a voltage reference producing two stable voltages of 3.5 V and 2.5 V which are directed to a control amplifier. This amplifier produces control signals for the current-source cells of a current-steering network utilizing a segmentation decoder for the three most significant bits, a collector-connected R/2R ladder for the intermediate bits, and an emitter-connected R/2R ladder for the remaining least significant bits. The control signals include one for setting the level of current through an NPN current-source transistor, a second for setting the level of current through a PMOS transistor for turning on or off a pair of switching transistors, and a third for establishing a bias voltage for the turn-on circuits for the NPN current-source transistor.

Abstract: An encoder (12) in an image-display system converts explicitly represented pixel values from an image source (14) into mix-run-encoded representations thereof and stores them into the locations of a display memory (16). A display mechanism (18) draws the resultant stored data from the display memory and interprets them in accordance with a mix-run-encoding scheme of a type previously used for anti-aliasing purposes. As a consequence, the system is able to provide a wide range of color shades with only modest-sized display and palette memories (16 and 36).

Abstract: An integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors, is disclosed. P-type dopant is implanted and diffused in an N-type substrate to form a sub-collector for a pnp transistor and also is implanted and diffused in the substrate to form a P-well for the sub-collector of an npn transistor. N-type material is then implanted and diffused into the P-well to form the npn sub-collector, and also is implanted in the substrate to form part of an isolation wall for the pnp transistor. A P-type epitaxial (epi) layer is grown over the N-type substrate. N-type material is implanted and diffused in the epi layer to complete the isolation wall for the pnp transistor, and to form the collector for the npn transistor. P-type and N-type material is implanted and diffused in the P-type epi layer to form the bases and emitters for the npn and pnp transistors.

Abstract: A separate filter circuit is inserted between the D/A converter and the summing junction in the feedback path of a conventional sigma delta modulator. This additional filter allows control of the quantization noise transfer function profile independently of the forward signal transfer function. By proper tailoring of the transfer functions a third or higher order modulator can be constructed without instability developing.

Abstract: An analog switching circuit may be implemented with MESFETs without forward biasing the switching device, and is applicable to JFET switches in general. Switching currents are provided from the nominal input line which closely tracks the true analog input voltage, but is segregated therefrom. A current supply fed from the nominal input line provides transient charging current to the gate of the switching transistor during the switching transition from OFF to ON states. Voltage setting devices hold the gate and source of the enhancement-mode current supply at approximately the nominal supply voltage level when the switching transistor is ON, while a control section holds the gate and source of the current supply device at a negative reference voltage level when the switching transistor is OFF. In either case, the current supply device is inhibited from delivering gate current to the switching transistor during steady state operation.

Abstract: A technique for "marking" integrated-circuit (IC) chips so that, when large lots of the chips are drift-tested at different temperatues, each chip can be identified positively so as to be associated with the test data accumulated for the particular chip. The technique includes forming additional resistors on each IC chip with the resistors connected in series and to a voltage supply. The resistors are timmed at the wafer stage to produce at nodal points between the resistors voltages having magnitudes which uniquely identify each particular chip, thereby to permit part-identified tests to be performed after the chips have been packaged as parts ready for shipment.

Abstract: The apparatus includes an operational amplifier which has inverting and non-inverting inputs and an output that is a function of the voltage at the inverting and non-inverting inputs. An attenuator network is connected to the operational amplifier. The attenuator network includes circuitry for reducing a voltage of a first value at the inputs of the attenuator network to a voltage that is a fraction of the first value at the output of the attenuator network which voltage is then transmitted to the operational amplifier inputs. The attenuator network includes additional circuitry for reducing a common-mode feed-through voltage of a second value at the inputs of the attenuator network to a common-mode feed-through voltage that is a fraction of the second voltage at the output of the operational amplifier.

Abstract: A pipelined multi-stage ADC in which residue signals are passed between stages as currents. All sample-and-hold circuits are designed to be current-in/current-out structures; all but one also provide a voltage output. A voltage representation of the analog signal is provided as input to the flash converter within the quantization loop of each stage, allowing implementation of a conventional voltage comparator architecture in the flash converter. An extra comparator is added to the flash converter and an extra segment is included in the DAC of each stage. Inputs above full scale and below zero can be converted and generate output codes. Whenever the input goes above full scale or below zero, an out-of-range bit is set and the digital outputs are set to all ones or all zeroes, respectively. The combination of out-of-range bit and digital codes tell whether overranging or underranging occurred.

Abstract: A three-terminal operational amplifier includes a current input, in addition to the conventional inverting and non-inverting inputs. The current input is inverted and added to the inverting input current, while its voltage is urged to a level equal to that of the inverting and non-inverting inputs. The new amplifier employs a pair of two-terminal operational amplifiers, the first of which has inverting and non-inverting inputs, and the second of which has the current input and a second input connected in common with an input to the first amplifier. Internal feedback circuits provide the desired current conveyance. The circuit may be implemented either with mutually discrete two-terminal operational amplifiers, or these elements may be merged into a single unified circuit. Applications include a general purpose adder/subtractor circuit, an inverting gain amplifier, an instrumentation amplifier, integrators and differentiators.

Abstract: A voltage-controlled delay is connected in series with a phase-locked loop. The voltage-controlled delay is controlled by the control voltage developed by the phase-locked loop amplifier and filter. With this arrangement, the amplifier and filter can be designed to have a transfer function that does not include an explicit zero. Consequently, the jitter transfer function of the overall structure can be designed to remain equal to or less than unity over all frequencies and jitter peaking is eliminated.

Abstract: High accuracy is achieved by employing, in conventional DAC architectures, very accurate current sources. To create these high-accuracy current sources, the outputs of several smaller, less accurate, nominally equal current sources are summed. A procedure is taught for selecting the number of current sources to achieve an arbitrary degree of accuracy with a desired level of confidence. Assuming the current sources are taken from a population whose output currents deviate from a design value according to a normal distribution, the minimum number of constituent current sources, n, required to provide an accurate total current is given by the formula n=(Z.sigma./E).sup.2, where Z is a number which corresponds to the probability that the output will fall within an error band E (i.e., a predetermined accuracy level) with a predetermined level of confidence, .sigma. is the standard deviation of the population.

Abstract: A signal conditioning circuit for an RTD includes feedback means to correct for the non-linear temperature characteristic of the RTD. The feedback means applies to the RTD a voltage which is a linear function of temperature, plus a fixed offset. The output signal from the circuit is proportional both to the RTD temperature and to the supply voltage. The resistors in the feedback system can be trimmed easily at a single temperature to calibrate the output. It can be combined with a metal film RTD on a single chip. The trimming can compensate for wide differences in RTD resistances.

Abstract: Wire-bonded IC chips are coated with siloxane polyimide and cured to a hardened state. The coating is applied over portions of the circuitry which are stress-sensitive. The coating is spaced away from the wire-bond regions of the chip. Thereafter, the coated chip is plastic encapsulated in conventional fashion.

Abstract: A phase-detector circuit for a phase-locked loop clock recovery system detects the phase difference between an information signal and a clock signal and produces a phase error signal representative of the phase difference. The phase detector includes, in one embodiment, five latches, serially interconnected, with the first latch receiving the information signal and each subsequent latch receiving the data output of the previous latch. The latches are enabled, in an alternating pattern, by the high-level and low-level portions of the clock signal. A first exclusive-OR (XOR) gate receives a delayed information signal and the data output of the second latch. A second XOR gate receives the data output of the second latch and the data output of the third latch. A third XOR gate receives the data output of the third latch and the data output of the fourth latch. A fourth XOR gate receives the data output of the fourth latch and the data output of the fifth latch.

Abstract: A fast, high-resolution A/D converter circuit includes a combination of a main-range up/down counter and a subrange A/D converter. An output from the up/down counter for upper bits is D/A-converted and subtracted from an input signal, and the remainder of subtraction is A/D-converted by the subrange A/D converter, thereby obtaining high-resolution conversion data. The circuit has a feedback loop which detects that the remainder becomes less than LSB of the up/down counter and stops a count operation. By discriminating that the remainder is more/less a predetermined level set higher than the LSB of the counter or outside/inside a predetermined range, a count rate is switched between high and low rates. The remainder enters subrange via the low rate count stage.

Abstract: Automatic test equipment (ATE) for post-production testing of multi-pin integrated circuits (ICs). Each pin is assigned to a pin card having a pin driver and an active load with the latter including both a current source and a current sink. The pin driver and active load are connectable alternatively to the IC pin in response to complementary inhibit signals. Within the active load, the source and sink and connected/disconnected by respective pairs of matched transistor switch circuits the individual switches of which are alternatively activatable by differential control means. Both switch circuits of each pair are supplied from a single current source. One switch circuit of each pair, when activated, directs the current from the single current source to (from) the IC pin, while the other switch circuit, when activated, directs the current to (from) a return line.

Abstract: A monolithic chip with an integrated circuit forming an 18-bit D/A converter powered by a single supply of .+-.5 volts. The circuit includes a voltage reference producing two stable voltages of 3.5V and 2.5V which are directed to a control amplifier. This amplifier produces control signals for the current-source cells of a current-steering network utilizing a segmentation decoder for the three most significant bits, a collector-connected R/2R ladder for the intermediate bits, and an emitter-connected R/2R ladder for the remaining least significant bits. The control signals include one for setting the level of current through an NPN current-source transistor, a second for setting the level of current through a PMOS transistor for turning on or off a pair of switching transistors, and a third for establishing a bias voltage for the turn-on circuits for the NPN current-source transistor.

Abstract: A digital-to-analog converter comprising a set of identical DAC cells each including: (1) a PNP bipolar current source transistor producing a continuous output current (equal values for all DAC cells), (2) a pair of PMOS switches connected to the collector of the bipolar transistor to divert the output current to either a ground line or a corresponding node of an R/2R ladder, (3) ladder circuitry for maintaining the full-scale ladder voltage below a predetermined level which keeps the PMOS switches in the saturated region of their characteristics, and (4) make-before-break switch control circuitry to close the PMOS switch being activated prior to opening the other PMOS switch.

Abstract: A converter for producing the function V.sub.out =V.sub.bias =V.sub.swing (1-2D), in which a DAC is combined with an operational amplifier and (typically) three or four resistors. A function of the voltage V.sub.swing, or a current corresponding thereto, is applied to the reference voltage input terminal of the DAC. The variable D is the DAC's digital input code, expressed as a decimal or fraction in the range between 0 and 1. The DAC output provides a suitably scaled and signed signal which is added to or subtracted from the offset signal V.sub.bias to produce V.sub.out.