Abstract: A band-gap voltage reference forming part of a CMOS IC chip. A .DELTA.V.sub.BE voltage is developed by stacked pairs of parasitic bipolar transistors, with the transistors of each pair operated at different current densities. MOS buffer transistors are connected at corresponding ends of the stacks where the .DELTA.V.sub.BE voltage is developed. The bipolar transistors are driven by MOS current sources.

Abstract: Voltage-to-Current (V-I) converters of the differential input and differential output type designed to be fabricated as an integrated circuit on a single monolithic chip. The circuit includes a first pair of resistors connected between first and second input terminals with their common node connected to the bases of a pair of NPN output transistors supplying differential output currents from their collectors. The emitters of these transistors are connected through corresponding resistors to the input terminals respectively. A capacitor is connected between the common bases and reference (ground) to establish an appropriate time constant for achieving high complementarily of the output currents. Variations on this basic circuit are disclosed for substantially eliminating input bias current and for reducing both odd and even-order distortion in the output signal.

Abstract: A magnetometer having only a single coil winding for sensing the magnetic field along a single axis. Functionally, the invention comprises an oscillator, an integrator, and a voltage-controlled current source. The oscillator uses a saturating inductor which also serves as the magnetic-field-sensing element. The inductor is driven with a positive voltage and when the current through the inductor exceeds a value which indicates that the core is saturated, the driving voltage switches to an equal-magnitude negative value. This negative drive is maintained until the current again indicates the core to be saturated, at which point the driving voltages switches back to the positive value. With no externally applied field, the inductor current averages to a zero value. An externally applied field helps the core saturate in one direction and hinders it in the other, resulting in a change in average inductor current.

Abstract: In an FET differential input, preferably using a quad set of devices according to the teaching of U.S. Pat. No. 3,729,660, the channel of each transistor is formed in a piecewise manner, of multiple segments. Each channel segment is associated with a corresponding drain segment (i.e., these are multi-drain devices). Each drain segment is connected in series with a thin-film resistor. The channel area associated with each drain segment can be selectively removed from the circuit by cutting the connected resistor with a laser. The device's channel area (and its effective width to length ratio, Z/L) is thereby alterable. The thin film resistors are cut as the offset is measured, until an acceptably low (effectively zero) offset is obtained. This trimming operation can be performed at room temperature, and yields not only a near zero offset voltage, but also near zero drift. CMRR, further, will be maximized. Neither operating current ratio nor drain voltage need be, or is, changed.

Abstract: A phase detector circuit is provided for correction of operation of a synchronous delay line clock generator. The phase detector includes multiple edge detectors. The multiple edge detectors provide an override of any corrective action by the rest of the phase detector to the synchronous delay line output, notwithstanding presence or absence of any phase error of less than 360.degree., if the phase position of the delay line output signal is off by an integral multiple of 360.degree.. Multiple taps from daisy-chained or series-connected delay line elements are provided to the multiple edge detectors. The multiple edge detectors compare the edge produced by each such tap against (in the first instance) one division of divided clock signal or (for each subsequent tap) the result of the previous such comparison. In each such case, the comparison is accomplished by a not R, not S flip-flop receiving the signals to be compared.

Abstract: A termination circuit for an R-2R ladder network for producing weighted currents, the 2R terminating resistor of the ladder being connected to an excitation source voltage which is 2(kT/q)ln 2 closer to the supply voltage than the emitter of the current source in the last (i.e., least significant) leg of the ladder. The excitation source is fabricated with just one type of bipolar transistor and does not require anamplifier or frequency compensation capacitor(s). The excitation source is a simple circuit requiring only five transistors, at least one of which has an emitter area which is a multiple of the emitter areas of the current source transistors. The base-emitter voltages of the transistors in the excitation source are connected in a voltage loop that goes from a voltage V.sub.LSB at the emitter of the current source transistor connected to the least significant ladder network shunt resistor to a voltage, Vt, which would be equal to V.sub.

Abstract: A high bandwidth chopper-stabilized amplifier operates main and auxiliary amplifiers at a randomized chopping signal frequency that substantially reduces intermodulation distortion between the input and chopping signals, clock noise and input voltage offset, thus making possible a significant increase in bandwidth. The circuit preferably uses a pseudo-random bit sequence generator to produce a pseudo-random chopping signal frequency.

Abstract: An interpolator circuit is formed from a chain of multiplexer/adder circuits. Each multiplexer/adder circuit selects one of the two multi-bit binary values which are to be interpolated in accordance with one bit of a multi-bit ratio value. The selected value is shifted and added to the output of a previous stage in the chain. When one of the two values is injected into the first stage, the final sum generated by the circuit chain is the interpolated value.

Abstract: A multi-port RAM register file adapted for flowing data directly from an input port of the register file to an output port of the register file and for simultaneously writing to a memory location in the register file. In addition to the RAM register, the apparatus includes, in a first embodiment, (1) first and second sets of multiplexers, the first set of multiplexers connected between the register file output ports on the one hand, and, on the other hand, the outputs of the second set of multiplexers and the RAM bit lines; the second set of multiplexers being connected between one input of the first set of multiplexers, as aforementioned, and the RAM register file input ports; and (3) flow-through address comparitors for controlling the multiplexers. The bit buses of the RAM are driven directly from the register file input ports.

Abstract: A wide dynamic range transconductance stage has two branches, each branch being composed of a plurality of transconductance circuit paths. Each circuit path has a greater transconductance than the other circuit paths for its branch within a respective sub-range of the input signal range for the stage as a whole, with each path dominating the other paths for its branch within its respective sub-range. The overall bandwidth for the stage, its g.sub.m, its noise characteristics and its input voltage range are enhanced as a result. Bandwidth and slew rate may be independently optimized by the designer. Two paths are used for each branch in the preferred embodiment, with one path consisting of a bipolar transistor and the other path either a field effect transistor or a resistor degenerated bipolar transistor. Multiple paths may be used based on the same principle.

Abstract: An audio power amplifier achieves a closed-loop bandwidth which is relatively independent of gain, and a very high slew rate capability, with a current feedback operational amplifier design. A separate operational amplifier which is connected as an integrator and operates at sub-audio frequencies compensates for the output terminal bias current of the first operational amplifier, thus mitigating the effects of current mirror mismatch in the current feedback circuit and allowing the overall output offset voltage to be significantly reduced.

Abstract: An apparatus for monitoring current through a lamp circuit that uses a series resistance shunt in the circuit with one end being connected to a current source and the second end being connected to the lamp. The circuitry includes a comparator that is connected across the shunt and has a threshold switching voltage such that a voltage across the shunt that is larger than the threshold voltage will switch the comparator on (as in the case where the lamp is not functioning) and a voltage across the shunt that is smaller than the threshold voltage (as in the case where the lamp is in the circuit and functioning) will switch the comparator off. In a preferred embodiment, the shunt is actually a portion of the printed circuit board trace.

Abstract: A differential input circuit has an input stage with a pair of differentially biased input transistors connected to supply current through respective load impedances, and a gain stage with a second pair of transistors connected to supply additional currents to the load impedances to keep the impedance currents constant over variations in the input voltage levels. A cross-coupled cascode circuit connected between the gain stage transistors and the load impedances compensates for inaccuracies in the load impedance currents which occur during dynamic operation of the circuit, and thus enhances gain, linearity and the current transfer efficiency between the two stages.

Abstract: A monolithic interface circuit for use with a linear variable differential transformer (LVDT) position transducer. The interface circuit includes a drive circuit for providing an excitation signal of selectable frequency and amplitude to the LVDT primary winding. The interface circuit further includes a decoder responsive to signals induced in the LVDT secondary windings for computing the position p of the LVDT core as a solution to the equation p=K(A-B)/(A+B), where A and B represent the signals induced in the primary winding and K is a constant scale factor. The decoder includes circuitry for rectifying and filtering the secondary signals, a charge balance loop responsive to the detected signals for providing a binary signal having a duty cycle representative of b/(A+B), and an output circuit responsive to the binary signal for providing the position output. The decoder provides excellent scale factor stability and linearity and is relatively insensitive to variations in primary drive amplitude.

Abstract: A JFET differential amplifier stage in which the gate-drain voltage of each input JFET is kept at least as great as the pinchoff voltage (V.sub.p), but preferably close to V.sub.p so as to reduce the effects of impact ionization and generation currents on the amplifier's input bias current. The input JFETs are cascoded with another pair of JFETs, and the gate-source circuits for the JFETs of each branch are connected in series with the gate-source circuit of an additional JFET between the gates and drains of the input JFETs. The additional JFET is supplied with a current that is substantially less than I.sub.DSS, and thus develops a significant portion of the necessary gate-drain voltages for the input JFETs. This enables a significant net reduction in the chip surface area occupied by the stage.

Abstract: An integrated-circuit (IC) chip formed with a capacitor comprising a lower layer of polysilicon clad with a thin film of TiSi.sub.2 serving as the lower plate of the capacitor, a layer of dielectric, a thin film of titanium nitride (TiN) on the upper surface of the dielectric to serve as the upper plate of the capacitor, a second layer of polysilicon (doped with phosphorous) over the TiN film, and metallization to make contact with the top plate of the capacitor.

Abstract: The foregoing objects are achieved in an assembly wherein the die attach paddle of a conventional leadframe is cut to form two electrically isolated die attach paddles and a dielectric tape is applied to one side of the two die attach paddles, spanning the space between them, providing physical support and substantially preventing cantilevered or twisting motion of the die attach paddles relative to the remainder of the leadframe assembly.

Abstract: A variable-gain amplifier including a ladder attenuator to which the input signal is applied. The ladder nodes develop progressively attenuated (reduced level) signals corresponding to the input signal. Controllable-transconductance (g.sub.m) stages are connected respectively to the ladder nodes, and a composite of their outputs is directed to a fixed-gain output amplifier. The transconductances of the g.sub.m stages are controlled by an interpolator circuit which steers a control current to each of the g.sub.m stages in sequence in response to an analog control signal as it is varied between minimum and maximum attenuation values. The control current activates each g.sub.m stage in sequence, raising the transconductance of each from effectively zero to maximum and then back to zero, in an overlapping fashion, so as to smoothly lower the overall gain of the variable-gain amplifier as the control signal is swept through its control range.

Abstract: A first Schottky diode is connected between the source of a first enhancement JFET and a low voltage line. The drain of the first enhancement JFET is connected through a first active load current source to a high voltage line, and also through a second Schottky diode and a second active load current source to the low voltage line. The first Schottky diode produces a voltage drop which maintains the source of the first enhancement JFET positive with respect to the low voltage line. The second Schottky diode produces a voltage drop complementary to that of the first Schottky diode, which causes the circuit to produce an output voltage across the second current source having a logically low level close to that of the low voltage line.

Abstract: In a voltage-switching digital-to-analog converter, each bit is switched by a switching circuit which uses a p-channel MOSFET as a V.sub.ref switch and an n-channel MOSFET as an Agnd switch, with a control circuit for controlling the signal applied to the gate of one of the devices (e.g., the n-channel device) to cause its "ON" resistance to match the "ON" resistance of the other device (e.g., the p-channel device). The control circuit includes reference n-channel and p-channel devices. A control signal is developed to drive the reference n-channel device to a condition wherein its drain current and drain-source voltage match those of the reference p-channel device, thereby causing their R.sub.ON s to match. The drive signal is taken as the output of the control means and is used to power the driver for the n-channel Agnd switches.