Abstract: A system includes a digital-to-analog converter circuit and a calibration circuit. The digital-to-analog converter circuit includes a gain control circuit providing volume adjustment. The system includes a calibration mode and a normal mode of operation. During calibration, a correction value associated with the gain control circuit is measured by the calibration circuit and stored. During normal operation, the stored correction value is combined with the input before provision of the same to the DAC circuit such that, for a predetermined input of midscale code, the desired system output remains constant despite any change in the volume setting of the gain control circuit.

Abstract: An emulation system used to debug software for a digital signal processor (DSP) includes a built-in digital signal analyzer which operates upon the same digital signals as those presented directly to and outputted by the DSP, bypassing the signal converters used to convert an input analog signal to digital format and the output digital signal to analog format. A host computer communicates with the digital signal analyzer via firmware in a control processor and personality board, or is alternately connected directly with the analyzer. Communications between the digital signal analyzer and the DSP are through the same contact probe as that used for the emulation software. The analyzer may be used to trigger a software function within the emulator based upon the real-time signal from the DSP, and is also capable of interpolating between successive digital values of an analyzed signal for display purposes.

Abstract: A maximum likelihood detector for a continuous time disk drive read channel includes a dynamic threshold updating circuit for a maximum likelihood detector using both positive and negative comparators for detecting the positive and negative peaks of an input signal; this includes comparing the input signal with at least one present dynamic threshold to produce positive and negative binary gating signals; a control circuit responsive to the binary gating signals, to the input signal, and to the peak detector circuit which identifies qualified input signal peaks; and a threshold update circuit responsive to the identification of qualified input signal peaks, which adjusts the present dynamic threshold by the difference between the input signal and the present dynamic threshold to obtain the next dynamic threshold.

Abstract: A method and apparatus for forming bridges between surfaces of a suspended microstructure and other surfaces of the suspended microstructure or particularly placed anchors on the die in order to increase the stiffness and lateral strength of the microstructure during fabrication. Once fabrication is completed, the bridges are cut by a laser thus fully releasing the microstructure into its final suspended and resilient condition.

Abstract: An IC chip formed with an analog-to-digital converter having a switched-capacitor programmable gain stage and employing a switched-capacitor sigma-delta modulator. The chip includes pins to receive a number of different audio input signals which are selectively connectible to buffer amplifiers the outputs of which are directed to a switch to select one output for further processing. The selected buffer amplifier output is d-c coupled to an input signal terminal of a switched-capacitor programmable gain stage. The output of this gain stage is coupled to an output stage including an op-amp and associated switched-capacitor circuitry. The programmable gain stage has a reference input terminal which is connected through an IC chip pin to an external capacitor the other electrode of which is returned to signal common.

Abstract: The n-bit coefficients of a FIR filter are encoded into m-bit digital words that represent selected bits of the original coefficients, where m is less than n, together with shift words that represent the order of the selected bits within the original n-bit coefficients. A software .sigma.-.DELTA. modulator is used to implement the encoding. The reduction in coefficient bits allows for a corresponding reduction in hardware multiplier capacity required to convolve the encoded coefficients with input data. The quantization error from the encoding is shaped to a higher frequency range that can later be filtered out. The coefficients are preferably encoded into a format that coincides with the data format employed by the multiplier, such as by using a Robertson's algorithm to encode to a modified Booth format.

Abstract: An output curvature correction is provided for a band-gap reference circuit that exhibits a temperature dependent output error in the form of k.sub.1 T - k.sub.2 Tln(k.sub.3 T) in the absence of the correction. A substantially constant collector current is driven through a correction transistor and used in connection with a proportional to absolute temperature (PTAT) transistor collector current in the uncorrected circuit. The difference between the base-emitter voltages for the two transistors has the form -k.sub.1 'T + k.sub.2 'ln(k.sub.3 'T.sub.). This voltage differential is scaled by an appropriate selection of resistor ratios and combined with the uncorrected circuit output to provide a corrected output that is substantially insensitive to temperature variations.

Abstract: An integrated circuit including a comparator having two output states and being responsive to a voltage developed across a shunt in the circuit so that the comparator assumes one of its two output states when the voltage developed across the shunt is greater than a threshold switching voltage and the other of its two output states when the voltage developed across the shunt is less than the threshold switching voltage. The integrated circuit additionally includes a threshold switching voltage sensitivity control circuit, coupled to and controlling the comparator, for controlling a sensitivity of the threshold switching voltage to changes in a supply voltage of the lamp circuit and for controlling a sensitivity of the threshold switching voltage to changes in temperature of the integrated circuit.

Abstract: An accelerometer comprising a microfabricated acceleration sensor and monolithically fabricated signal conditioning circuitry. The sensor comprises a differential capacitor arrangement formed by a pair of capacitors. Each capacitor has two electrodes, one of which it shares electrically in common with the other capacitor. One of the electrodes (e.g., the common electrode) is movable and one of the electrodes is stationary in response to applied acceleration. The electrodes are all formed of polysilicon members suspended above a silicon substrate. Each of the capacitors is formed of a plurality of pairs of electrode segments electrically connected in parallel and, in the case of the movable electrodes, mechanically connected to move in unison. When the substrate is accelerated, the movable electrodes move such that the capacitance of one of the capacitors increases, while that of the other capacitor decreases.

Abstract: A logarithmic amplifier gain stage for supplying, in response to an instantaneous input signal, an output signal representing a portion of a corresponding logarithmic value of the input signal. The gain stage includes a transistor amplifier having an input that receives the input signal and an intermediate output that supplies an intermediate output signal. A full-wave detector having an input coupled to the intermediate output of the transistor amplifier receives the intermediate output signal and supplies the output signal wherein the detector includes a rectifier comprising transistors having different effective emitter areas. The different emitter areas can be formed by physical differences in emitter area of the full-wave rectifier transistors. In another embodiment of the invention, the different emitter areas can be synthesized by controlling a voltage between a base and an emitter of at least one transistor in the full-wave rectifier.

Abstract: A D-to-A converter of the type having a number of current sources each connected to a pair of switches operable by binary control pulses for directing the source current either to the output line or to ground. Power to operate the DAC is reduced by special control circuitry which opens both switches of any given switch pair whenever two successive control pulses call for the output-line switch to be open.

Abstract: Signal-sampling apparatus wherein information signals are directed to a register under the control of first clock pulses and are latched into the register under the control of second clock pulses. A calibrator monitors the timing of the first and second clock pulses to determine if they are so close together that data signals subsequently output from the register will be distorted so as to cause errors in downstream devices. If such condition is found, the calibrator inverts the phase of the second clock pulses to assure proper time spacing to avoid data corruption.

Abstract: An input buffer circuit incorporates variable hysteresis levels to protect against unintended changes of output state in response to glitches in the input signal. The circuit is used in connection with input signals that alternate between LO and HI input states with known minimum periods between alternations. The switching threshold hysteresis for reverting back to a prior output state is boosted during the period following an input signal transition, with the boosted hysteresis removed following a delay period that is no greater than the minimum period between successive input signal transitions. Numerous circuit designs may be used to implement the varying hysteresis levels.

Abstract: A voltage attenuation network includes one or more cascaded resistor ladder stages, with decremented voltage taps provided at successive cascaded steps within each stage. Each stage includes a termination step having a resistance value Ri equal to the stage input impedance, series step resistors with resistance values Ri(1-A)/A and shunt step resistors with resistance values Ri/(1-A), where A is a step-to-step voltage attenuation factor. The input resistances of each step within a given stage are substantially equal, eliminating the need for output buffers at the step taps. A pair of switches are provided for each step, including an output switch connected between the step input node and a common output line, and a shunt switch connected in series with the shunt resistor for that step. Only one output switch is closed at a time, and only the corresponding shunt switch for the same step is opened.

Abstract: An apparatus for monitoring voltage as a function of temperature of a storage battery and an apparatus for controlling the charging voltage of the battery based on battery temperature, voltage, and charging system loads. The battery monitoring apparatus includes a comparator for comparing, at any temperature in the working temperature range of the battery, the actual battery voltage with a reference battery voltage. The reference battery voltage is the voltage gassing curve for the storage battery. The comparator is given a temperature coefficient provided by a temperature-sensitive band-gap voltage reference. A plurality of the temperature-sensitive band-gap reference cells may be connected together in order to accurately track any differently sloped battery gassing voltage curve.

Abstract: Gain linearity problems caused by impact ionization in a active MOS device are avoided by connecting an MOS shield device in series with the active MOS device so that the overall supply voltage is split across two devices, keeping both devices in a region of operation well below where impact ionization becomes a significant problem. The gate of the MOS shield device is maintained at a voltage proportional to its drain voltage, thereby keeping the device in the saturation mode and avoiding an abrupt mode change associated with prior art shield circuits.

Abstract: A monolithic interface circuit for use with a linear variable differential transformer (LVDT) position transducer. The interface circuit includes a drive circuit for providing an excitation signal of selectable frequency and amplitude to the LVDT primary winding. The interface circuit further includes a decoder responsive to signals induced in the LVDT secondary windings for computing the position p of the LVDT core as a solution to the equation p=K(A-B)/(A+B), where A and B represent the signals induced in the primary winding and K is a constant scale factor. The decoder includes circuitry for rectifying and filtering the secondary signals, a charge balance loop responsive to the detected signals for providing a binary signal having a duty cycle representative of B/(A+B), and an output circuit responsive to the binary signal for providing the position output. The decoder provides excellent scale factor stability and linearity and is relatively insensitive to variations in primary drive amplitude.

Abstract: The invention comprises a method for fabricating a monolithic chip containing integrated circuitry as well as a suspended polysilicon microstructure. The inventive method comprises 67 processes which are further broken down into approximately 330 steps. The processes and their arrangement allow for compatible fabrication of transistor circuitry and the suspended polysilicon microstructure on the same chip.

Abstract: The gain of a folded cascode operational amplifier is enhanced by connecting the current circuits of added compensation transistors to supply the current circuits of pre-existing gain transistors. Changes in the current through the primary gain transistor resulting from a change in the output load produce approximately equal changes in the base currents of both the primary gain and primary compensation transistors. The change in the compensation transistor's base current is transmitted through the amplifier circuitry to supply the change in the gain transistor's base current, rather than forcing a change in the input voltage differential to supply this current. The differential input signal is thus less sensitive to changes in the output, resulting in higher transconductance and gain.

Abstract: A switched capacitor one-bit digital-to-analog converter is preferably utilized in the feedback path of a sigma delta modulator. The one-bit digital-to-analog converter includes first and second capacitors, a first switching circuit for coupling charge from a reference source to the capacitors, and a second switching circuit for coupling charge from the capacitors to positive and negative outputs, such as the summing junction of an operational amplifier. The switches in the second switching circuit have a cross-coupled configuration and are controlled by data dependent control signals. The data dependent control signals are structured such that charge is coupled from the capacitors to the summing junction on both clock phases, regardless of the state of the data. As a result, the sizes of the capacitors can be reduced by a factor of two for the same charge transfer.