Abstract: A digital oversampling digital-to-analog converter system includes an interpolator, a sigma-delta modulator, a digital-to-analog converter and a low pass filter. The interpolator receives a digital input signal and upsamples the input signal by certain upsampling factor. The upsampled signal is processed by the sigma-delta modulator, converted to an analog signal by the digital-to-analog converter and then filtered by the low pass filter. The interpolator includes control circuitry, preferably a central processor, which controls the upsampling factor and increases the upsampling factor upon a decrease in the frequency of the input signal.

Abstract: A separate filter circuit is inserted between the D/A converter and the summing junction in the feedback path of a conventional sigma delta modulator. This additional filter allows control of the quantization noise transfer function profile independently of the forward signal transfer function. By proper tailoring of the transfer functions a third or higher order modulator can be constructed without instability developing. The modulator can also be constructed as a completely digital circuit and used as a noise shaping circuit in a digital digital-to-analog converter.

Abstract: A process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors, and a novel chip made by such a process. P-type dopant is implanted and diffused in an N-type substrate to form a sub-collector for a pnp transistor and also is implanted and diffused in the substrate to form a P-well for the sub-collector of an npn transistor. N-type material is then implanted and diffused into the P-well to form the npn sub-collector, and also is implanted in the substrate to form part of an isolation wall for the pnp transistor. A P-type epitaxial (epi) layer is grown over the N-type substrate. N-type material is implanted and diffused in the epi layer to complete the isolation wall for the pnp transistor, and to form the collector for the npn transistor. P-type and N-type material is implanted and diffused in the P-type epi layer to form the bases and emitters for the npn and pnp transistors.

Abstract: The effective capacity of an instruction cache in a digital signal processor with a modified HARVARD architecture is enhanced by decoding a current instruction to be executed to determine whether it is a program memory data access (PMDA) instruction that requires a data transfer from the program memory when the next instruction is fetched from the program memory. If it is a PMDA instruction, the next instruction is loaded into a cache, which then provides the stored instruction each time the PMDA instruction reappears. This relieves a bottleneck resulting from a simultaneous call for both the next instruction, and datum for the current instruction, from the program memory. The cache is used only for an instruction following a PMDA instruction, and can thus have a substantially smaller capacity than previously.

Abstract: A synchronous progressive-compression type logarithmic amplifier includes one or two channels of amplifier/limiter stages and a corresponding multi-stage synchronous demodulator circuit to provide low noise and/or low power operation as well as other useful operational modes. A preferred embodiment of the invention includes two channels in which the input of a first amplifier stage in each channel forms a logarithmic amplifier input. The synchronous demodulator circuit is realized as a number of multiplier stages each having a first input coupled to the output of a corresponding amplifier stage in the first channel, a second input coupled to the output of a corresponding amplifier stage in the second channel, and a current output. A current summing bus is coupled to the current outputs of each of the multiplier stages, and forms the logarithmic amplifier output.

Abstract: A dynamically selectable multimode pulse width modulation system includes ramp generator means for generating a ramp; pulse edge modulation means responsive to the ramp generator means for defining a leading edge modulated pulse, a trailing edge modulated pulse and a dual edge modulated pulse; and mode selection means responsive to the pulse edge modulation means for selecting one of the leading edge modulation, trailing edge modulation, and dual edge modulation modes of pulse width modulation.

Abstract: A bandgap voltage reference circuit includes a low temperature coefficient of resistance (TCR) tail resistor connected in series with a high TCR tail resistor, and a low TCR correction resistor connected in parallel with the high TCR resistor. The ratio of resistance values for the parallel resistors is selected to produce a correction voltage that essentially cancels a Tln(T) output deviation from temperature linearity, where T is absolute temperature. Matching voltage-temperature characteristics are obtained by selecting a resistor ratio at which the rate of change in the circuit's output voltage, both with and without the parallel resistors, is substantially zero at approximately the same temperature. While the shape of the compensation voltage-temperature curve is determined by the resistor ratio, it is scaled to the magnitude of the Tln(T) deviation by an appropriate selection of absolute resistor values. The correction resistor is preferably a trimmable thin film element.

Abstract: In an integrated circuit package, a ROM is provided for identifying the device for testing purposes. The ROM is programmed, for example, by cutting resistor links. The resistor links set the output of the PROM. This output is a binary word which is read by the tester at the same time that the tester performs measurements on the reference device. With this information the tester can then perform various calculations.

Abstract: A multiplexed single channel knock sensor signal conditioner system for internal combustion engines includes a plurality of sensors for sensing the vibrations associated with knocking in an internal combustion engine; a single signal conditioning channel for providing a signal level representative of the magnitude of the knock; and means for selectively connecting the sensors to the signal conditioning channel. The signal conditioning channel includes a band pass filter, the frequency characteristics of which are adjusted according to the sensor connected to the signal conditioning channel.

Abstract: A ring-type oscillator with a plurality of delay cells including differential pairs of MOS transistors. Current sources supply current to each pair, and the magnitude of the current supplied is variable by a control voltage to alter the delay of the MOS devices, thereby to alter the frequency of oscillation. Each delay cell MOS device is connected in series with another MOS device biased into its linear region to act as a load resistance. This load is variable by the control voltage so as to tend to maintain the gain of the delay cells constant with changes in frequency of oscillation.

Abstract: In a pixel display system, a plug-to-plug compatible pixel decoder palette is provided which is responsive to a predetermined sequence of commands on an I/O data channel to switch the mode of operation of the pixel decoder palette. The pixel coder palette comprises a random access memory used as a look-up table to store colors to be displayed and the I/O channel is used to store new colors in or read colors out from the random access memory. The different modes of operation of the pixel decoder palette involve operating on intensity values represented by 6-bit bytes and 8-bit bytes and involve continuous edge graphics wherein pixels bridging boundaries between objects are displayed as mixes of the colors on each side of the boundary.

Abstract: An automatic calibration for a ramp voltage generator includes a ramp voltage generator circuit responsive to a clock signal for providing a ramp voltage during a ramp voltage period; a comparator responsive to the ramp voltage for indicating whether the ramp voltage has reached a predetermined reference voltage level in the ramp voltage period; and a ramp rate control circuit responsive to the comparator for adjusting the ramp voltage generator circuit to drive the ramp voltage to obtain the predetermined reference voltage level in the ramp voltage period.

Abstract: An all CMOS voltage comparator circuit which incorporates a strobed latch. A strobe signal precharges the entire circuit to a known state which is independent of the input voltages and in which substantially no static current is drawn. Under static conditions after the circuit has been strobed, the source coupled pair is virtually disconnected from the supply voltage(s) and draws almost no current, as well. When the circuit is strobed, a source coupled FET pair amplifies the differential input signal, with positive feedback provided through a pair of cross coupled PMOS load transistors, as well as cross coupled NMOS cascode transistors. The source coupled pair feeds a pair of output buffers, or drivers, whose FETs are sized such that a "low" voltage level is generated on both outputs until the source-coupled pair resolves the input voltage difference (i.e., the differential input voltage exceeds the switching threshold). At that time, the outputs become complementary digital levels and are usable.

Abstract: A complementary bipolar process enables both PNP and NPN transistors to be added to a CMOS process with a minimum of extra fabrication steps. The P-well of a CMOS process is used for the collector region of the PNP transistor and the "down isolation" for the NPN transistor. A buried P diffusion provides "up" isolation for the NPN transistor and buried collector for the PNP transistor. A method for increasing the NPN buried collector to "up" isolation breakdown voltage is described which uses multiple N type impurities.

Abstract: A current-output CMOS DAC with a compensation circuit to increase output impedance. The circuit includes an auxiliary MOS current source matched to at least one of the DAC bit-current sources. A comparator compares the drain voltage of the main MOS current source (which is connected to an external reference current source I.sub.ref) with the drain voltage of the auxiliary current source. The output of the comparator controls the magnitude and sign of a correction current which is directed to the main current source transistor and thereby alters the bit-current output to reduce the ouput sensitivity to changed conditions.

Abstract: An auto-TC voltage reference wherein an operational amplifier receives at one input the voltage of a Zener diode and at its other input receives a compensation signal from a feedback circuit comprising a transistor and resistor network. When one of the resistors of the network is trimmed to give a nominal output voltage for the reference, the TC of the reference voltage will have been reduced to zero, or nearly so. The circuitry is capable of compensating Zener diodes of either positive or negative TC.

Abstract: A trimmable resistor network including a plurality of series-connected sections each including a plurality of paralleled link resistors each capable of being cut so as to be eliminated from the network, the paralleled resistors in each section having resistance values such that the section resistance changes by at least approximately integral multiples of a fixed amount when the resistors are cut.

Abstract: A charge pump circuit for providing a bipolar voltage output at substantially double the unipolar voltage input source includes first and second voltage input terminals; a first and a second capacitor; a first switching device for selectively connecting first and second capacitors across the input terminals to charge each to the voltage of the input source; first and second voltage output terminals; a second switching device for selectively connecting the capacitors in series between one of the input terminals and one of the output terminals to generate a first polarity voltage which is substantially double the voltage of the input source; a third switching device for selectively connecting at least one of the capacitors in series between the other of the input terminals and the other of the output terminals to generate a second polarity voltage which is substantially double the voltage of the input source; and a clock for sequentially, selectively actuating the first, second and third switching devices.

Abstract: A programmable gain amplifier including first and second gain elements are connected by an impedance selector which allows programmability of the gain of both gain elements. The impedance selector is connected in series with the output of the first gain element. The impedance selector places an impedance in the feedback path of the first gain element or the input path of the second gain element. Errors introduced in the signal path due to the switches are attenuated by the open loop gain of the first gain element. The gain may be equally divided between both stages of the amplifier to allow for optimum band width. Optimum noise performance may be obtained by placing most of the gain in the first stage. An instrumentation amplifier may also be made which further includes a third gain element connected to the gain element with a second impedance selector in a manner similar to the connection of the first gain element to the second gain element.

Abstract: An electronic switch with very low dynamic "on" resistance includes an operational transconductance amplifier including a non-inverting input adapted for connection to a reference potential and an inverting input interconnected with the amplifier output; and control means for enabling the amplifier output to provide a low-impedance virtual potential at the inverting input approximately the same as that of the reference potential and for disabling the amplifier output to promote a high impedance at the inverting input.