Patents Assigned to Analog Technologies, Inc.
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Publication number: 20080291711Abstract: A freewheeling DC/DC step-down converter includes a high-side MOSFET, an inductor and an output capacitor connected between the input voltage and ground. A freewheeling clamp, which includes a freewheeling MOSFET and diode, is connected across the inductor. When the high-side MOSFET is turned off, a current circulates through the inductor and freewheeling clamp rather than to ground, improving the efficiency of the converter. The converter has softer diode recovery and less voltage overshoot and noise than conventional Buck converters and features unique benefits during light-load conditions.Type: ApplicationFiled: April 21, 2008Publication date: November 27, 2008Applicant: Advanced Analogic Technologies, Inc.Inventor: Richard K. Williams
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Publication number: 20080290450Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.Type: ApplicationFiled: July 30, 2008Publication date: November 27, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
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Publication number: 20080290911Abstract: A gate driver for a power MOSFET in, for example, a DC-DC converter switches the MOSFET between a fully-on condition and a low-current condition instead of switching the MOSFET between fully-on and fully-off conditions. The amount of charge that must be transferred to charge and discharge the gate of the MOSFET is thereby reduced, and the efficiency of the MOSFET is improved. A feedback circuit may be used to assure that the magnitude of current in the power MOSFET in its low-current condition is correct. Alternatively, a trimming process may be used to correct the magnitude of the voltage supplied by the gate driver to the gate of the power MOSFET in the low-current condition.Type: ApplicationFiled: August 8, 2007Publication date: November 27, 2008Applicant: Advanced Analogic Technologies, Inc.Inventor: Richard K. Williams
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Publication number: 20080290452Abstract: A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped region diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer is formed at an interface between an epitaxial layer and a substrate, at a location generally below the dopant in the mesa.Type: ApplicationFiled: July 31, 2008Publication date: November 27, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
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Publication number: 20080290449Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.Type: ApplicationFiled: July 30, 2008Publication date: November 27, 2008Applicant: Advanced Analogic Technologies, Inc.Inventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
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Publication number: 20080293214Abstract: A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped region diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer is formed at an interface between an epitaxial layer and a substrate, at a location generally below the dopant in the mesa.Type: ApplicationFiled: July 31, 2008Publication date: November 27, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
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Publication number: 20080290451Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.Type: ApplicationFiled: July 30, 2008Publication date: November 27, 2008Applicant: Advanced Analogic Technologies, Inc.Inventors: Richard K. Williams, Donald Ray Disney, Jun-Wei Chen, Wal Tien Chan, HyungSik Ryu
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Patent number: 7456622Abstract: The low voltage circuit for starting up a synchronous step-up DC/DC converter, which connects to a voltage source through an inductor, includes a P-type power transistor, an N-type power transistor and a controller. The P-type power transistor includes a body diode, and one end of the P-type power transistor acts as a power source of an oscillator. The N-type power transistor connects the P-type power transistor in series, and both of the power transistors are not enabled at the same time. The oscillator electrically connects to the controller, which enables the P-type power transistor at initialization time, and enables the N-type power transistor a period after the initialization time.Type: GrantFiled: April 10, 2007Date of Patent: November 25, 2008Assignee: Advanced Analog Technology, Inc.Inventors: Mao Chuan Chien, Chu Yu Chu, Yu Min Sun
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Patent number: 7449380Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.Type: GrantFiled: February 25, 2005Date of Patent: November 11, 2008Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
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Patent number: 7445979Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall and which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.Type: GrantFiled: April 5, 2006Date of Patent: November 4, 2008Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
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Patent number: 7446621Abstract: The switching method between pulse frequency modulation and pulse width modulation signals is first based on an output voltage of a power transistor to generate a corresponding pulse frequency modulation signal. Next, it is determined whether the corresponding pulse frequency modulation signal has reached its maximal frequency. If so, the initial pulse width modulation signal is adjusted to have the same width as the pulse frequency modulation signal. Thereafter, the adjusted pulse width modulation signal is outputted.Type: GrantFiled: June 6, 2007Date of Patent: November 4, 2008Assignee: Advanced Analog Technology, Inc.Inventors: Li Chieh Chen, Yu Min Sun, Chu Yu Chu
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Publication number: 20080254592Abstract: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.Type: ApplicationFiled: April 30, 2008Publication date: October 16, 2008Applicant: Advanced Analogic Technologies, Inc.Inventor: Richard K. Williams
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Patent number: 7432555Abstract: A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection circuitry functional to protect the MOSFET. Before connecting the bonding pads together, the ESD protection circuitry and/or the MOSFET can be separately tested. A voltage higher than functioning ESD protection circuitry would permit can be used when testing the MOSFET. A packaging process such as wire bonding or attaching the die to a substrate in a flip-chip package can connect the bonding pads after testing.Type: GrantFiled: May 5, 2005Date of Patent: October 7, 2008Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
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Publication number: 20080237656Abstract: An isolation structure for a semiconductor device comprises a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate. An isolated junction field-effect transistor is formed in the isolated pocket.Type: ApplicationFiled: December 17, 2007Publication date: October 2, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
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Publication number: 20080237706Abstract: A lateral MOSFET formed in a substrate of a first conductivity type includes a gate formed atop a gate dielectric layer over a surface of the substrate, a drain region of a second conductivity type, a source region of a second conductivity type, and a body region of the first conductivity type which extends under the gate. The body region may have a non-monotonic vertical doping profile with a portion located deeper in the substrate having a higher doping concentration than a portion located shallower in the substrate. The lateral MOSFET may be drain-centric, with the source region and an optional dielectric-filled trench surrounding the drain region.Type: ApplicationFiled: December 17, 2007Publication date: October 2, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
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Publication number: 20080237783Abstract: A bipolar transistor is formed in an isolation structure comprising a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate.Type: ApplicationFiled: December 17, 2007Publication date: October 2, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
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Publication number: 20080237704Abstract: An isolation structure for a semiconductor device comprises a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate. A MOSFET is formed in the isolated pocket.Type: ApplicationFiled: December 17, 2007Publication date: October 2, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
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Publication number: 20080237782Abstract: An isolated diode comprises a floor isolation region, a dielectric-filled trench and a sidewall region extending from a bottom of the trench at least to the floor isolation region. The floor isolation region, dielectric-filled trench and a sidewall region are comprised in one terminal (anode or cathode) of the diode and together form an isolated pocket in which the other terminal of the diode is formed. In one embodiment the terminals of the diode are separated by a second dielectric-filled trench and sidewall region.Type: ApplicationFiled: December 17, 2007Publication date: October 2, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
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Publication number: 20080230812Abstract: Various integrated circuit devices, in particular a junction field-effect transistor (JFET), are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described.Type: ApplicationFiled: February 27, 2008Publication date: September 25, 2008Applicant: Advanced Analogic Technologies, Inc.Inventors: Donald R. Disney, Richard K. Williams
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Publication number: 20080217729Abstract: An isolated CMOS pair of transistors formed in a P-type semiconductor substrate includes an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains a P-channel MOSFET in an N-well and an N-channel MOSFET in a P-well. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.Type: ApplicationFiled: February 14, 2008Publication date: September 11, 2008Applicant: Advanced Analogic Technologies, Inc.Inventors: Donald R. Disney, Richard K. Williams
