Patents Assigned to Analog Technologies, Inc.
  • Patent number: 7656132
    Abstract: A battery charger apparatus for charging a battery, comprises a charge-current control circuit for receiving a charge-current control signal to control an amount of charge current being drawn from an input source, e.g.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: February 2, 2010
    Assignee: Advanced Analogic Technologies, Inc.
    Inventors: John Sung Ko So, David Alan Brown
  • Patent number: 7626243
    Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: December 1, 2009
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Donald Ray Disney, Jun-Wei Chen, Richard K. Williams, HyungSik Ryu, Wai Tien Chan
  • Patent number: 7622902
    Abstract: An LDO with over-current protection includes a first and a second P-type transistor, a sensing resistor, a comparator, and an error amplifier. The channel aspect ratio of the first P-type transistor is much higher than that of the second P-type transistor. The first P-type transistor generates output voltage source according to input voltage source and current control signal. The sensing resistor is coupled among the input voltage source, the second P-type transistor, and the comparator, providing a sensing voltage. The comparator generates a current limiting signal according to first reference voltage and the sensing voltage. When the current limiting signal enables the error amplifier, the error amplifier adjusts voltage of the current control signal according to second reference voltage and voltage divided from the output voltage source; when the current limiting signal disables the error amplifier, voltage of the current control signal is not adjusted.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: November 24, 2009
    Assignee: Advanced Analog Technology, Inc.
    Inventors: Shun-Hau Kao, Mao-Chuan Chien
  • Patent number: 7616145
    Abstract: A switched capacitor circuit includes a first level-crossing detector to generate a level-crossing detection signal when an input signal crosses a first predetermined level. A first waveform generator generates a first predetermined waveform and a second waveform generator generates a second predetermined waveform. A second level-crossing detector generates a second level-crossing detection signal when said second predetermined waveform crosses a voltage reference level a second time. A second switch is coupled to the second level-crossing detector, and a third switch is coupled to the first level-crossing detector. The second switch turns OFF when the second level-crossing detection signal indicates the second predetermined waveform crossed the voltage reference level a second time. The third switch turns OFF when the first level-crossing detection signal indicates the input signal crossed the first predetermined level.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: November 10, 2009
    Assignee: Cambridge Analog Technologies, Inc.
    Inventor: Hae Seung Lee
  • Patent number: 7612549
    Abstract: An LDO with fast current limit includes P-type transistor, an error amplifier, an adjustable reference voltage circuit for generating an adjustable reference voltage, and an N-type transistor. The P-type transistor includes a first end coupled to the input voltage source, a second end for outputting an output voltage source, and a control end for receiving a current control signal in order to control the current of the output voltage source. The error amplifier generates the current control signal according to the reference voltage and a voltage divided from the output voltage source. N-type transistor includes a first end coupled to the output end of the error amplifier, a second end coupled to the input voltage source, and a control end for receiving the adjustable reference voltage. When the N-type transistor is turned on, the voltage of the current control signal is clamped by the adjustable reference voltage.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: November 3, 2009
    Assignee: Advanced Analog Technology, Inc.
    Inventors: Shun-Hau Kao, Mao-Chuan Chien
  • Patent number: 7612543
    Abstract: A feedback signal sensing method includes the steps of: providing a pulse width modulation (PWM) signal having a period; charging a capacitor by a current source during a pulse duration of the period, so as to form an equivalent slope compensation ramp signal; conducting an inductor current flowing from a boost inductor to flow through an equivalent resistor during the pulse duration of the period, so as to form an equivalent inductor current signal; and using a coupling characteristic of the capacitor together with the equivalent slope compensation ramp signal and the equivalent inductor current signal to form a feedback signal.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: November 3, 2009
    Assignee: Advanced Analog Technology, Inc.
    Inventors: Chien Peng Yu, Yi Cheng Wang, Ye Hsuan Yan
  • Patent number: 7608895
    Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: October 27, 2009
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chen
  • Patent number: 7605432
    Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: October 20, 2009
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chen
  • Patent number: 7605428
    Abstract: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: October 20, 2009
    Assignee: Advanced Analogic Technologies, Inc.
    Inventors: Richard K. Williams, Donald Ray Disney
  • Patent number: 7605433
    Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: October 20, 2009
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chen
  • Patent number: 7602024
    Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: October 13, 2009
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chen
  • Patent number: 7602023
    Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: October 13, 2009
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chen
  • Publication number: 20090236683
    Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.
    Type: Application
    Filed: May 28, 2009
    Publication date: September 24, 2009
    Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan, Jun-Wei Chen, HyungSik Ryu
  • Patent number: 7592228
    Abstract: In a trench-gated MOSFET including an epitaxial layer over a substrate of like conductivity and trenches containing thick bottom oxide, sidewall gate oxide, and conductive gates, body regions of the complementary conductivity are shallower than the gates, and clamp regions are deeper and more heavily doped than the body regions but shallower than the trenches. Zener junctions clamp a drain-source voltage lower than the FPI breakdown of body junctions near the trenches, but the zener junctions, being shallower than the trenches, avoid undue degradation of the maximum drain-source voltage. The epitaxial layer may have a dopant concentration that increases step-wise or continuously with depth. Chained implants of the body and clamp regions permits accurate control of dopant concentrations and of junction depth and position. Alternative fabrication processes permit implantation of the body and clamp regions before gate bus formation or through the gate bus after gate bus formation.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: September 22, 2009
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
  • Publication number: 20090225484
    Abstract: Devices, such as mobile devices, may be exposed to short circuit and output overload events. To protect against such events, mobile devices typically include current limit circuits. Some current limit circuits may involve user programmable function. User programmable function may need accurate current limit detectors. One approach to improving resolution and accuracy of current limit detectors using a single resistive device is to magnify the operating current range. Various embodiments of the present invention include devices and methods for detecting pre-programmed current limits.
    Type: Application
    Filed: March 10, 2009
    Publication date: September 10, 2009
    Applicant: Advanced Analogic Technologies, Inc.
    Inventor: John So
  • Publication number: 20090215237
    Abstract: A lateral trench MOSFET includes a trench containing a device segment and a gate bus segment. The gate bus segment of the trench is contacted by a conductive plug formed in a dielectric layer overlying the substrate, thereby avoiding the need for the conventional surface polysilicon bridge layer. The conductive plug is formed in a substantially vertical hole in the dielectric layer. The gate bus segment may be wider than the device segment of the trench. A method includes forming a shallow trench isolation (STI) while the conductive material in the trench is etched.
    Type: Application
    Filed: April 29, 2009
    Publication date: August 27, 2009
    Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Donald Ray Disney, Cho Chiu Ma
  • Patent number: 7576525
    Abstract: Charge storage devices (e.g., batteries or supercapacitors) need to be charged from time to time. In an apparatus, to protect a charge storage device as well as the supply used to charge it, the apparatus typically includes power loop control circuitry. One approach to implementing the power loop control employs a temperature sensor in combination with soft start circuitry in order to protect the circuitry from a rapidly increasing temperature when charge current increases. The soft start circuitry allows for controlled step-wise increase and regulation of the current. The approach preferably allows for selecting the number and resolution of such incremental steps. Various embodiments of the invention include devices and methods for controlling power and may take into account temperature in step-wise regulation of the charge current.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: August 18, 2009
    Assignee: Advanced Analogic Technologies, Inc.
    Inventors: John So, David Yen Wai Wong
  • Patent number: 7576391
    Abstract: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: August 18, 2009
    Assignee: Advanced Analogic Technologies, Inc.
    Inventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
  • Patent number: 7573105
    Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: August 11, 2009
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chen
  • Patent number: 7551008
    Abstract: The circuit for fixing the peak current of an inductor includes an operating current, a ramp-type boost converter and a comparator. The magnitude of the operating current is proportional to that of the voltage source of the inductor. The ramp-type boost converter is connected to the operating current. One input end of the comparator is connected to a reference voltage, and the other end is connected to the output of the ramp-type boost converter. The output of the comparator is connected to the gate of a power transistor, which controls the turn-on time of the inductor.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: June 23, 2009
    Assignee: Advanced Analog Technology, Inc.
    Inventors: Mao Chuan Chien, Chu Yu Chu, Yu Min Sun