Abstract: Horizontal gate-all-around devices and methods of manufacturing are described. The hGAA devices comprise a fully-depleted silicon-on-insulator (FD-SOI) under the channel layers in the same footprint as the hGAA. The buried dielectric insulating layer of the FD-SOI comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-k material, and the buried dielectric insulating layer has a thickness in a range of from 0 nm to 10 nm.
Type:
Application
Filed:
January 25, 2022
Publication date:
August 4, 2022
Applicant:
Applied Materials, Inc.
Inventors:
Ashish Pal, El Mehdi Bazizi, Benjamin Colombeau, Myungsun Kim
Abstract: Aspects of the present disclosure provide systems and apparatuses for a substrate processing assembly with a laminar flow cavity gas injection for high and low pressure. A dual gas reservoir assembly is provided in a substrate processing chamber, positioned within a lower shield assembly. A first gas reservoir is in fluid communication with a processing volume of the substrate processing assembly via a plurality of gas inlet, positioned circumferentially about the processing volume. A second gas reservoir is positioned circumferentially about the first gas reservoir, coupled therewith via one or more reservoir ports. The second gas reservoir is in fluid communication with a first gas source. A recursive path gas assembly is positioned in an upper shield body adjacent to an electrode to provide one or more gases to a dark space gap.
Type:
Application
Filed:
February 3, 2021
Publication date:
August 4, 2022
Applicants:
Applied Materials, Inc., Applied Materials, Inc.
Abstract: Methods of doping a semiconductor material are disclosed. Some embodiments provide for conformal doping of three dimensional structures. Some embodiments provide for doping with high concentrations of boron for p-type doping.
Abstract: Embodiments disclosed herein include a method of determining the position of a sensor wafer relative to a pedestal. In an embodiment, the method comprises placing a sensor wafer onto the pedestal, wherein the sensor wafer comprises a first surface that is supported by the pedestal, a second surface opposite the first surface, and an edge surface connecting the first surface to the second surface, wherein a plurality of sensor regions are formed on the edge surface, and wherein the pedestal comprises a major surface and an annular wall surrounding the sensor wafer. In an embodiment, the method further comprises determining a gap distance between each of the plurality of sensor regions and the annular wall. In an embodiment, the method may further comprise determining a center-point offset of a center-point of the sensor wafer relative to a center point of the annular wall from the gap distances.
Abstract: Methods of depositing a metal film with high purity are discussed. A catalyst enhanced CVD process is utilized comprising an alkyl halide catalyst soak and a precursor exposure. The precursor comprises a metal precursor having the general formula (I): M-L1(L2)y, wherein M is a metal, L1 is an aromatic ligand, L2 is an aliphatic ligand, and y is a number in the range of from 2 to 8 to form a metal film on the substrate surface, wherein the L2 comprises 1,5-hexdiene, 1,4-hexadiene, and less than 5% of 1,3-hexadiene. Selective deposition of a metal film with high purity on a metal surface over a dielectric surface is described.
Type:
Grant
Filed:
January 4, 2021
Date of Patent:
August 2, 2022
Assignee:
Applied Materials, Inc.
Inventors:
Byunghoon Yoon, Seshadri Ganguli, Xi Cen
Abstract: Embodiments include a modular microwave source. In an embodiment, the modular microwave source comprises a voltage control circuit, a voltage controlled oscillator, where an output voltage from the voltage control circuit drives oscillation in the voltage controlled oscillator. The modular microwave source may also include a solid state microwave amplification module coupled to the voltage controlled oscillator. In an embodiment, the solid state microwave amplification module amplifies an output from the voltage controlled oscillator. The modular microwave source may also include an applicator coupled to the solid state microwave amplification module, where the applicator is a dielectric resonator.
Abstract: Disclosed are approaches for forming a semiconductor device. In some embodiments, a method may include a method may include providing a semiconductor device including plurality of patterning structures over a device stack, each of the plurality of patterning structures including a first sidewall, a second sidewall, and an upper surface. The method may further include forming a seed layer along just the first sidewall and the upper surface of each of the plurality of patterning structures, forming a metal layer atop the seed layer, forming a fill material between each of the plurality of patterning structures, and removing the plurality of patterning structures.
Type:
Grant
Filed:
October 16, 2020
Date of Patent:
August 2, 2022
Assignee:
Applied Materials, Inc.
Inventors:
Sony Varghese, M. Arif Zeeshan, Shantanu Kallakuri, Kelvin Chan
Abstract: Examples of the present technology include semiconductor processing methods that provide a substrate in a substrate processing region of a substrate processing chamber, where the substrate is maintained at a temperature less than or about 50° C. An inert precursor and a hydrocarbon-containing precursor may be flowed into the substrate processing region of the substrate processing chamber, where a flow rate ratio of the inert precursor to the hydrocarbon-containing precursor may be greater than or about 10:1. A plasma may be generated from the inert precursor and the hydrocarbon-containing precursor, and a carbon-containing material may be deposited from the plasma on the substrate. The carbon-containing material may include diamond-like-carbon, and may have greater than or about 60% of the carbon atoms with sp3 hybridized bonds.
Type:
Grant
Filed:
August 7, 2020
Date of Patent:
August 2, 2022
Assignee:
Applied Materials, Inc.
Inventors:
Huiyuan Wang, Rick Kustra, Bo Qi, Abhijit Basu Mallick, Kaushik Alayavalli, Jay D. Pinson
Abstract: A crested barrier memory and selector device may include a first electrode, a first self-rectifying, tunneling layer having a first dielectric constant, and an active, barrier layer that has a second dielectric constant and another self-rectifying, tunneling layer having a third dielectric constant. The first self-rectifying layer may be between the first electrode and the active layer. The second dielectric constant may be at least 1.5 times larger than the first dielectric constant. The device may also include a second electrode, where the active, barrier layer is between the first self-rectifying, tunneling layer and the second electrode.
Abstract: An additive manufacturing apparatus includes an environmentally sealed first chamber, a second chamber separated from the first chamber by a first valve, a platform positionable in the first chamber, a dispenser configured to deliver a plurality of successive layers of feed material onto the platform in the first chamber, at least one energy source to selectively fuse feed material in a layer on the platform in the first chamber, and an air knife assembly to direct a laminar flow of air across a layer of feed material on the platform in the first chamber. The air knife assembly includes an inlet module and an exhaust module that are movable through the first valve between the first chamber and the second chamber.
Abstract: The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.
Type:
Grant
Filed:
November 20, 2020
Date of Patent:
August 2, 2022
Assignee:
Applied Materials, Inc.
Inventors:
Peng Suo, Ying W. Wang, Guan Huei See, Chang Bum Yong, Arvind Sundarrajan
Abstract: A load port system includes an isolation compartment coupled to an equipment front end module (EFEM). Reactive gas is to be removed from the isolation compartment. The load port system further includes an elevator disposed in the isolation compartment. The elevator is coupled to an elevator arm that extends from the isolation compartment into the EFEM through an opening to raise and lower a carrier opener within the EFEM.
Type:
Grant
Filed:
November 9, 2020
Date of Patent:
August 2, 2022
Assignee:
Applied Materials, Inc.
Inventors:
Luke W. Bonecutter, David T. Blahnik, Paul B. Reuter
Abstract: A light-emitting device includes a plurality of light-emitting diodes, a first cured composition over a first subset of the light-emitting diodes, and a second cured composition over a second subset of light-emitting diodes. The first cured composition includes a first photopolymer and a blue photoluminescent material that is an organic, organometallic, or polymeric material, embedded in the first photopolymer. The second cured composition includes a second photopolymer and a nanomaterial embedded in the second photopolymer. The nanomaterial is selected to emit red or green light in response.
Type:
Grant
Filed:
August 28, 2020
Date of Patent:
August 2, 2022
Assignee:
Applied Materials, Inc.
Inventors:
Yingdong Luo, Lisong Xu, Sivapackia Ganapathiappan, Hou T. Ng, Byung Sung Kwak, Mingwei Zhu, Nag B. Patibandla
Abstract: Disclosed are rare earth metal containing silicate coatings, coated articles (e.g., heaters and susceptors) or bodies of articles and methods of coating such articles with a rare earth metal containing silicate coating.
Type:
Grant
Filed:
June 18, 2019
Date of Patent:
August 2, 2022
Assignee:
Applied Materials, Inc.
Inventors:
Xiao-Ming He, Cheng-Hsuan Chou, Jennifer Y. Sun
Abstract: Methods of forming a DRAM bit line to improve line edge roughness (LER) and lower resistance are described. The method comprises implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed.
Type:
Application
Filed:
April 11, 2022
Publication date:
July 28, 2022
Applicant:
Applied Materials, Inc.
Inventors:
Lequn Liu, Priyadarshi Panda, Jonathan C. Shaw
Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a substrate; a multilayer stack of reflective layers on the substrate; a capping layer on the multilayer stack of reflecting layers; and an absorber layer on the capping layer, the absorber layer comprising an alloy of molybdenum (Mo) and antimony (Sb).
Abstract: Apparatuses and methods to provide a patterned substrate are described. A plurality of patterned and spaced first lines and carbon material lines and formed on the substrate surface by selectively depositing and etching films extending in a first direction and films extending in a second direction that crosses the first direction to pattern the underlying structures.
Type:
Application
Filed:
April 14, 2022
Publication date:
July 28, 2022
Applicant:
Applied Materials, Inc.
Inventors:
Tejinder Singh, Takehito Koshizawa, Abhijit Basu Mallick, Pramit Manna, Nancy Fung, Eswaranand Venkatasubramanian, Ho-Yung David Hwang, Samuel E. Gottheim
Abstract: Methods for gap filling features of a substrate surface are described. Each of the features extends a distance into the substrate from the substrate surface and have a bottom and at least one sidewall. The methods include depositing a non-conformal film in the feature of the substrate surface with a plurality of high-frequency ratio-frequency (HFRF) pulses. The non-conformal film has a greater thickness on the bottom of the features than on the at least one sidewall. The deposited film is substantially etched from the sidewalls of the feature. The deposition and etch processes are repeated to fill the features.
Abstract: Methods of producing grating materials with variable height are provided. In one example, a method may include providing a grating material atop a substrate, and positioning a shadow mask between the grating material and an ion source, wherein the shadow mask is separated from the grating material by a distance. The method may further include etching the grating material using an ion beam passing through a set of openings of the shadow mask, wherein a first depth of a first portion of the grating material is different than a second depth of a second portion of the grating material.
Type:
Application
Filed:
April 18, 2022
Publication date:
July 28, 2022
Applicant:
Applied Materials, Inc.
Inventors:
Joseph C. Olson, Morgan Evans, Thomas Soldi, Rutger Meyer Timmerman Thijssen, Maurice Emerson Peploski