Abstract: A method for enhancing the depth of focus process window during a lithography process includes applying a photoresist layer comprising a photoacid generator on a material layer disposed on a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and dynamically changing a frequency of the electric field as generated while providing the thermal energy to the photoresist layer.

Abstract: Exemplary deposition methods may include forming a plasma of an oxygen-containing precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include, while maintaining the plasma of the oxygen-containing precursor, flowing a silicon-containing precursor into the processing region of the semiconductor processing chamber at a first flow rate. The methods may include ramping the first flow rate of the silicon-containing precursor over a period of time to a second flow rate greater than the first flow rate. The methods may include depositing a silicon-containing material on the semiconductor substrate.

Abstract: Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.

Abstract: Embodiments described herein relate to a lower side wall for use in a processing chamber. a lower side wall for use in a processing chamber is disclosed herein. The lower side wall includes an inner circumference, an outer circumference, a top surface, a plurality of flanges, and a first concave portion. The outer circumference is concentric with the inner circumference. The plurality of flanges project from the inner circumference. The first concave portion includes a plurality of grooves arranged along a circumferential direction of the lower side wall. Each groove has an arc shape such that the plurality of grooves concentrate a gas when the gas contacts the plurality of grooves.

Abstract: Exemplary semiconductor processing methods include forming a via in a semiconductor structure. The via may be defined in part by a bottom surface and a sidewall surface formed in the semiconductor structure around the via. The methods may also include depositing a tantalum nitride (TaN) layer on the bottom surface of the via. In embodiments, the TaN layer may be deposited at a temperature less than or about 200° C. The methods may still further include depositing a titanium nitride (TiN) layer on the TaN layer. In embodiments, the TiN layer may be deposited at a temperature greater than or about 300° C. The methods may additionally include depositing a fill-metal on the TiN layer in the via. In embodiments, the metal may be deposited at a temperature greater than or about 300° C.

Abstract: A processing method comprises positioning a substrate in a processing chamber and setting a temperature of the substrate to a range of 50° C. to 500° C.; conducting an atomic layer deposition (ALD) cycle on the substrate; and repeating the ALD cycle to form a silicon oxide film. The ALD cycle comprises: exposing the substrate to an aminosilane precursor in the processing chamber by pulsing a flow of the aminosilane precursor; purging the processing chamber of the aminosilane precursor; exposing the substrate to an oxidizing agent by pulsing a flow of the oxidizing agent for a duration in a range of greater than or equal to 100 milliseconds to less than or equal to 3 seconds; and purging the processing chamber of the oxidizing agent.

Abstract: Methods for pre-cleaning substrates having metal and dielectric surfaces are described. The substrate is exposed to a strong reductant to remove contaminants from the metal surface and damage the dielectric surface. The substrate is then exposed to an oxidation process to repair the damage to the dielectric surface and oxidize the metal surface. The substrate is then exposed to a weak reductant to reduce the metal oxide to a pure metal surface without substantially affecting the dielectric surface. Processing tools and computer readable media for practicing the method are also described.

Abstract: Exemplary deposition methods may include introducing hydrogen into a processing chamber, a powder disposed within a processing region of the processing chamber. The method may include striking a first plasma in the processing region, the first plasma including energetic hydrogen species. The method may include exposing the powder to the energetic hydrogen species in the processing region. The method may include chemically reducing the powder through a reaction of the powder with the energetic hydrogen species. The method may include removing process effluents including unreacted hydrogen from the processing region. The method may also include forming a layer of material on grains of the powder within the processing region.

Abstract: Methods of depositing a metal film by exposing a substrate surface to a halide precursor and an organosilane reactant are described. The halide precursor comprises a compound of general formula (I): MQzRm, wherein M is a metal, Q is a halogen selected from Cl, Br, F or I, z is from 1 to 6, R is selected from alkyl, CO, and cyclopentadienyl, and m is from 0 to 6. The aluminum reactant comprises a compound of general formula (II) or general formula (III): wherein R1, R2, R3, R4, R5, R6, R7, R8, Ra, Rb, Rc, Rd, Re, and Rf are independently selected from hydrogen (H), substituted alkyl or unsubstituted alkyl; and X, Y, X?, and Y? are independently selected from nitrogen (N) and carbon (C).

Abstract: Exemplary methods of producing a semiconductor substrate may include plating a metal within a plurality of vias on the semiconductor substrate. A target average fill thickness of the metal within the plurality of vias may be between about a thickness equal to an average via radius of the plurality of vias and a thickness twice the average via radius of the plurality of vias. At least one via of the plurality of vias may be filled to a height below the target average fill thickness of the metal. The methods may include heating the metal to cause reflow of the metal within each via of the plurality of vias. The reflow may adjust the metal within the at least one via to increase in height towards the target average fill thickness.

Abstract: Methods for depositing molybdenum films on a substrate are described. The substrate is exposed to a molybdenum halide precursor and an aluminum precursor to form the molybdenum film (e.g., elemental molybdenum) at a low temperature. The exposures can be sequential or simultaneous.

Abstract: A method is disclosed for operating an endpoint detection system of a processing chamber having a ceiling formed therein, a substrate support located internal to the processing chamber, and a substrate resting on the substrate support. A transparent panel is located in the ceiling of the processing chamber, the panel oriented at a first acute angle relative to the substrate and the substrate support. The transparent panel receives an incident light beam from the endpoint detection system at a second acute angle relative to the panel. The transparent panel transmits the incident light beam to the substrate within the processing chamber at an angle perpendicular to the substrate and the substrate support.

Abstract: Apparatus and methods for measuring surface topography are described. The analysis apparatus and methods detect light reflected from the reflective backside of a cantilever assembly including a tip, calculate a background level (BGL) value obtained from an optical scan of a reference sample using a power spectral density (PSD) value obtained from a topographical scan of a reference sample to generate a correlational coefficient between the BGL and the PSD values. The correlational coefficient between the BGL and PSD values is used to measure the BGL value of additional EUV mask blanks by a topographical scan of the EUV mask blanks using the same tip mounted to the cantilever.

Abstract: There is provided a method and a system configured to obtain an image of a one or more first areas of a semiconductor specimen acquired by an examination tool, determine data Datt informative of defectivity in the one or more first areas, determine one or more second areas of the semiconductor specimen for which presence of a defect is suspected based at least on an evolution of Datt, or of data correlated to Datt, in the one or more first areas, and select the one or more second areas for inspection by the examination tool.

Abstract: In one embodiment, a method may include providing a substrate, comprising a plurality of surface features, an isolation layer, disposed between the plurality of surface features, and a substrate base, disposed subjacent the isolation layer and the plurality of surface features, wherein the plurality of surface features extend above a surface of the isolation layer. The method may include directing a low energy ion beam to the substrate, when the substrate is heated at a targeted temperature, wherein an altered layer is formed within an outer portion of the isolation layer, and wherein an inner portion of the isolation layer is not implanted.

Abstract: Embodiments of the present disclosure generally relate to hardmasks and to processes for forming hardmasks by plasma-enhanced chemical vapor deposition (PECVD). In an embodiment, a process for forming a hardmask layer on a substrate is provided. The process includes introducing a substrate to a processing volume of a PECVD chamber, the substrate on a substrate support, the substrate support comprising an electrostatic chuck, and flowing a process gas into the processing volume within the PECVD chamber, the process gas comprising a carbon-containing gas. The process further includes forming, under plasma conditions, an energized process gas from the process gas in the processing volume, electrostatically chucking the substrate to the substrate support, depositing a first carbon-containing layer on the substrate while electrostatically chucking the substrate, and forming the hardmask layer by depositing a second carbon-containing layer on the substrate.

Abstract: The present disclosure generally relates to methods for selectively etching copper, cobalt, and/or aluminum layers on a substrate semiconductor manufacturing applications. A substrate comprising one or more copper layers, cobalt layers, or aluminum layers is transferred to a processing chamber. The surface of the copper, cobalt, or aluminum layer is oxidized. The oxidized copper, cobalt, or aluminum surface is then exposed to hexafluoroacetylacetonate vapor. The hexafluoroacetylacetonate vapor reacts with the oxidized copper, cobalt, or aluminum surface to form a volatile compound, which is then pumped out of the chamber. The reaction of the oxidized copper, cobalt, or aluminum surface with the hexafluoroacetylacetonate vapor selectively atomic layer etches the copper, cobalt, or aluminum surface.

Abstract: A plasma reactor includes a chamber body having an interior space that provides a plasma chamber and having a ceiling, a gas distributor to deliver a processing gas to the plasma chamber, a pump coupled to the plasma chamber to evacuate the chamber, a workpiece support to hold a workpiece, and an intra-chamber electrode assembly. The intra-chamber electrode assembly includes an insulating frame, a first plurality of coplanar filaments that extend laterally through the plasma chamber between the ceiling and the workpiece support along a first direction, and a second plurality of coplanar filaments that extend in parallel through the plasma chamber along a second direction perpendicular to the first direction. Each filament of the first and second plurality of filaments includes a conductor at least partially surrounded by an insulating shell. A first RF power source supplies a first RF power to the conductor of the intra-chamber electrode assembly.

Abstract: A component for a processing chamber includes a ceramic body having at least one surface with a first average surface roughness. The component further includes a conformal protective layer on at least one surface of the ceramic body, wherein the conformal protective layer is a plasma resistant rare earth oxide film having a substantially uniform thickness of less than 300 ?m over the at least one surface and having a second average surface roughness that is less than the first average surface roughness.

Abstract: Disclosed herein are methods for reducing MOSFET trench sidewall surface roughness. In some embodiments, a method includes providing a device structure including a well formed in an epitaxial layer, forming a plurality of trenches through the well and the epitaxial layer, and implanting the device structure to form a treated layer along a sidewall of just an upper portion of the device structure within each of the plurality of trenches. The method may further include etching the device structure to remove the treated layer.