Abstract: Methods for filling a substrate feature with a seamless gap fill are described. Methods comprise forming a metal film a substrate surface, the sidewalls and the bottom surface of a feature, the metal film having a void located within the width of the feature; treating the metal film with a plasma; and annealing the metal film to remove the void.

Abstract: Methods and film stacks for extreme ultraviolet (EUV) lithography are described. The film stack comprises a substrate with a hard mask, bottom layer, middle layer and photoresist. Etching of the photoresist is highly selective to the middle layer and a modification of the middle layer allows for a highly selective etch relative to the bottom layer.

Abstract: Disclosed herein are methods for forming split-gate MOSFETs including a gate shield. In some embodiments, a method may include providing a device structure including a well formed in an epitaxial layer, forming a set of trenches through the well and the epitaxial layer, implanting the device structure to form a gate shield layer at a bottom of each of the set of trenches, and forming a gate spacer layer over the device structure including within the set of trenches.

Abstract: A method includes receiving a plurality of operations in a sequence recipe. The plurality of operations are associated with processing a plurality of substrates in a substrate processing system. The method further includes identifying a plurality of completion times corresponding to the plurality of operations. Each completion time of the plurality of completion times corresponds to completion of a respective operation of the plurality of operations. The method further includes simulating the plurality of operations by setting a virtual time axis to each of the plurality of completion times to generate a schedule for the sequence recipe. The method further includes causing, based on the schedule, the plurality of substrates to be processed or performance of a corrective action.

Abstract: Embodiments described herein relate to ground path systems providing a shorter and symmetrical path for radio frequency (RF) energy to propagate to a ground to reduce generation of the parasitic plasma. The ground path system bifurcates the processing volume of the chamber to form an inner volume that isolates an outer volume of the processing volume.

Abstract: Methods and systems of detection of wafer de-chucking in a semiconductor processing chamber are disclosed. Methods and systems of interdiction are also disclosed to prevent hardware and wafer damage during semiconductor fabrication if and when de-chucking is detected. In one embodiment, a de-chucking detection method is based on measuring change in imaginary impedance of a plasma circuit, along with measuring one or both of reflected RF power and arc count. In another embodiment, a possibility of imminent de-chucking is detected even before complete de-chucking occurs by analyzing the signature change in imaginary impedance.

Abstract: Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts through the selective deposition of a fill material.

Abstract: A physical vapor deposition system includes a chamber, three target supports to targets, a movable shield positioned having an opening therethrough, a workpiece support to hold a workpiece in the chamber, a gas supply to deliver nitrogen gas and an inert gas to the chamber, a power source, and a controller. The controller is configured to move the shield to position the opening adjacent each target in turn, and at each target cause the power source to apply power sufficient to ignite a plasma in the chamber to cause deposition of a buffer layer, a device layer of a first material that is a metal nitride suitable for use as a superconductor at temperatures above 8° K on the buffer layer, and a capping layer, respectively.

Abstract: Exemplary methods of etching semiconductor substrates may include flowing a fluorine-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having an exposed region of a first silicon-containing material and an exposed region of a second silicon-containing material. The second silicon-containing material may be exposed within a recessed feature defined by the substrate. The methods may include flowing a silicon-containing precursor into the processing region of the semiconductor processing chamber. The methods may include forming a plasma within the processing region of the semiconductor processing chamber to generate plasma effluents of the fluorine-containing precursor and the silicon-containing precursor. The methods may include contacting the substrate with the plasma effluents. The methods may include removing at least a portion of the second silicon-containing material.

Abstract: Embodiments described herein relate to a substrate support assembly which enables a cryogenic temperature operation of an electrostatic chuck (ESC) so that a substrate disposed thereon is maintained at a cryogenic processing temperature suitable for processing while other surfaces of a processing chamber are maintained at a different temperature. The substrate support assembly includes an electrostatic chuck (ESC), an ESC base assembly coupled to the ESC having a refrigerant channel disposed therein, and a facility plate having a coolant channel disposed therein. The facility plate includes a plate portion and a flange portion. The plate portion is coupled to the ESC base assembly and the flange portion coupled to the ESC with a seal assembly. A vacuum region is defined by the ESC, the ESC base assembly, the plate portion of the facility plate, the flange portion of the facility plate, and the seal assembly.

Abstract: Disclosed is a semiconductor processing approach wherein a wafer twist is employed to increase etch rate, at select locations, along a hole or space end arc. By doing so, a finished hole may more closely resemble the shape of the incoming hole end. In some embodiments, a method may include providing an elongated contact hole formed in a semiconductor device, and etching the elongated contact hole while rotating the semiconductor device, wherein the etching is performed by an ion beam delivered at a non-zero angle relative to a plane defined by the semiconductor device. The elongated contact hole may be defined by a set of sidewalls opposite one another, and a first end and a second end connected to the set of sidewalls, wherein etching the elongated contact hole causes the elongated contact hole to change from an oval shape to a rectangular shape.

Abstract: Methods of surface pretreatment during selective deposition are disclosed. One or more embodiment of the disclosure provides surface pretreatments which facilitate the removal of blocking layers. Some embodiments of the disclosure include a surface pretreatment comprising exposure of a substrate with a first surface and a second surface to modify the first surface, a blocking layer is deposited on the modified first surface, a film is selectively deposited on the second surface over the blocking layer, and the blocking layer is removed.

Abstract: Methods for DRAM device with a buried word line are described. The method includes forming a metal cap layer and a molybdenum conductor layer in a feature on a substrate. The method includes depositing the metal cap layer on the substrate by physical vapor deposition (PVD) and depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer.

Abstract: Methods for depositing a metal contact stack on a substrate are described. The method stack includes a metal cap layer and a molybdenum conductor layer. The method includes depositing the metal cap layer on the substrate by physical vapor deposition (PVD) and depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer.

Abstract: Dinuclear molybdenum coordination complexes are described. Methods for depositing molybdenum-containing films on a substrate are described. The substrate is exposed to a dinuclear molybdenum precursor and a reactant to form the molybdenum-containing film (e.g., elemental molybdenum, molybdenum oxide, molybdenum carbide, molybdenum silicide, molybdenum nitride). The exposures can be sequential or simultaneous.

Abstract: Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, forming an oxide layer over the device structure including within each of the plurality of trenches and over a top surface of the device structure, and implanting a first portion of the oxide layer using an ion implant delivered to the device structure at a non-zero angle of inclination relative to a perpendicular extending from a top surface of the device structure. The method may further include removing the oxide layer from the top surface of the device structure and from a sidewall of each of the plurality of trenches, wherein a second portion of the oxide layer remains along a bottom of each of the plurality of trenches.

Abstract: There is provided a system and method of resource verification for an application, the method comprising: obtaining a checklist of resources required for running the application, wherein the checklist is generated by: obtaining source code and an executable file of the application; running the executable file, and monitoring resources accessed by the application during execution thereof and corresponding access type of each resource, giving rise to a first list of resources; performing static code analysis of the source code including searching the source code for one or more specific code patterns indicative of respective resources to be accessed and corresponding access types thereof, and generating a second list of resources; and mapping the first list and second list of resources to generate the checklist of resources. The method further comprises automatically verifying the checklist of resources, giving rise to a verification result.

Abstract: Aspects of the disclosure relate to apparatus for the fabrication of waveguides. In one example, an angled ion source is utilized to project ions toward a substrate to form a waveguide which includes angled gratings. In another example, an angled electron beam source is utilized to project electrons toward a substrate to form a waveguide which includes angled gratings. Further aspects of the disclosure provide for methods of forming angled gratings on waveguides utilizing an angled ion beam source and an angled electron beam source.

Abstract: Exemplary methods of semiconductor processing may include forming a plasma of a fluorine-containing precursor. The methods may include performing a chamber clean in a processing region of a semiconductor processing chamber. The processing region may be at least partially defined between a faceplate and a substrate support. The methods may include generating aluminum fluoride during the chamber clean. The methods may include contacting surfaces within the processing region with a carbon-containing precursor. The methods may include volatilizing aluminum fluoride from the surfaces of the processing region.

Abstract: Techniques for deposition of high-density dielectric films for patterning applications are described. More particularly, a method of processing a substrate is provided. The method includes flowing a precursor-containing gas mixture into a processing volume of a processing chamber having a substrate positioned on an electrostatic chuck. The substrate is maintained at a pressure between about 0.1 mTorr and about 10 Torr. A plasma is generated at the substrate level by applying a first RF bias to the electrostatic chuck to deposit a dielectric film on the substrate. The dielectric film has a refractive index in a range of about 1.5 to about 3.