Abstract: Embodiments disclosed herein include a sensor wafer. In an embodiment, the sensor wafer comprises a substrate, wherein the substrate comprises a first surface, a second surface opposite the first surface, and an edge surface between the first surface and the second surface. In an embodiment, the sensor wafer further comprises a plurality of sensor regions formed along the edge surface, wherein each sensor region comprises a self-referencing capacitive sensor.

Abstract: An apparatus, system and method. An apparatus may include an RF power assembly, arranged to output an RF signal; a resonator, coupled to receive the RF signal, the resonator comprising a first output end and a second output end, and a drift tube assembly, configured to transmit an ion beam, and coupled to the resonator. As such, the drift tube assembly may include a first AC drift tube electrode, coupled to the first output end, and a second AC drift tube electrode, coupled to the second output end and separated from the first AC drift tube by a first gap. The RF power assembly may be switchable to switch output from a first Eigenmode frequency to a second Eigenmode frequency.

Abstract: Embodiments of the present disclosure generally relate to a lift pin assembly used for de-chucking substrates. The lift pin assembly includes a base and one or more lift pin holders. Each lift pin holder includes a first portion and a second portion. The first portion is coupled to the base by a metal connector and the second portion is coupled to the first portion by a metal connector. A resistor is disposed in the first portion of the lift pin holder. The second portion includes a lift pin support for supporting a lift pin. The lift pin, the lift pin support, and the metal connectors are electrically conductive. The base is connected to a reference voltage, such as the ground, forming a path for the residual electrostatic charge in the substrate from the substrate to the reference voltage.

Abstract: A system and method for specimen examination, the system comprising a processing and memory circuitry (PMC) for: obtaining an image of at least a part of a specimen, the image acquired by an examination tool; receiving one or more characteristics of a defect of interest and a location of interest associated therewith; modifying within the image one or more pixels corresponding to the location of interest, wherein the modification is provided in accordance with a characteristic of the defect of interest, thereby planting the defect of interest into the image; processing the modified image to detect locations of potential defects of the specimen in accordance with a detection recipe; and determining whether the detected locations include the location of interest. Subject to the location of interest not being detected, modifying the detection recipe to enable detecting the planted defect of interest at the location of interest.

Abstract: A method includes identifying a bottleneck operation of a plurality of operations in a sequence recipe. The plurality of operations are associated with transporting and processing a plurality of substrates in a substrate processing system. The method further includes determining, based on the bottleneck operation, a takt time for the plurality of substrates. The takt time is an amount of time between a first substrate entering the substrate processing system and a second substrate entering the substrate processing system. The method further includes determining a plurality of queue times. Each of the plurality of queue times corresponds to a respective operation of the plurality of operations. The method further includes causing, based on the takt time and the plurality of queue times, the plurality of substrates to be processed by the substrate processing system.

Abstract: Exemplary methods of forming semiconductor structures may include forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor. The methods may include forming a silicon nitride layer from a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor. The silicon nitride layer may be characterized by an oxygen concentration greater than or about 5 at. %. The methods may also include repeating the forming a silicon oxide layer and the forming a silicon nitride layer to produce a stack of alternating layers of silicon oxide and silicon nitride.

Abstract: Exemplary methods of semiconductor processing may include delivering a carbon-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include generating a plasma of the carbon-containing precursor and the hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include forming a layer of graphene on a substrate positioned within the processing region of the semiconductor processing chamber. The substrate may be maintained at a temperature below or about 600° C. The methods may include halting flow of the carbon-containing precursor while maintaining the plasma with the hydrogen-containing precursor.

Abstract: A substrate support pedestal comprises an electrostatic chuck, a cooling base, a gas flow passage, a porous plug, and a sealing member. The electrostatic chuck comprises body having a cavity. The cooling base is coupled to the electrostatic chuck via a bond layer. The gas flow passage is formed between a top surface of the electrostatic chuck and a bottom surface of the cooling base. The gas flow passage further comprises the cavity. The porous plug is positioned within the cavity to control the flow of gas through the gas flow passage. The sealing member is positioned adjacent to the porous plug and is configured to form one or more of a radial seal between the porous plug and the cavity and an axial seal between the porous plug and the cooling base.

Abstract: An embodiment is a processing system for processing a substrate. The processing system includes a Front Opening Unified Pod (FOUP) load lock (FLL) and a vacuum system. The FLL has walls defining an interior space therein. The FLL includes load lock isolation and tunnel isolation doors. The load lock isolation door is operable to close a first opening in a first sidewall of the FLL. The first opening is sized so that a FOUP is capable of passing therethrough. The tunnel isolation door is operable to close a second opening in a second sidewall of the FLL. The second opening is sized so that a substrate is capable of passing therethrough. The vacuum system is fluidly connected to the interior space of the FLL and is operable to pump down a pressure of the interior space of the FLL.

Abstract: A system of classifying a pattern of interest (POI) on a semiconductor specimen, where the system includes a processor and memory circuitry configured to obtain a high-resolution image of the POI, and generate data usable for classifying the POI in accordance with a defectiveness-related classification. Generating the data utilizes a machine learning model that has been trained in accordance with training samples. The training samples include a high-resolution training image captured by scanning a respective training pattern on a specimen, the respective training pattern being similar to the POI, and a label associated with the image. The label is derivative of low-resolution inspection of the respective training pattern.

Abstract: A magnetic levitation system for contactlessly holding and moving a carrier in a vacuum chamber, including a base defining a transportation track, a carrier movable above the base along the transportation track, and at least one magnetic bearing for generating a magnetic levitation force between the base and the carrier. The at least one magnetic bearing includes a first magnet unit arranged at the base and a second magnet unit arranged at the carrier. The magnetic levitation system further includes a magnetic side stabilization device for stabilizing the carrier in a lateral direction, the magnetic side stabilization device comprising a stabilization magnet unit arranged at the base, wherein at least one of the first magnet unit and the first stabilization magnet unit is arranged in a housing space of the base, the housing space being separated from an inner volume of the vacuum chamber by a separation wall.

Abstract: Disclosed are 3-D DRAM devices and methods of forming 3-D DRAM devices. One method may include forming a stack of DRAM device layers, forming a MOS substrate directly atop the stack of alternating DRAM device layers, and forming a trench through the MOS substrate and the stack of DRAM device layers. The method may further include depositing a protection layer over the MOS substrate, wherein the protection layer is deposited at a non-zero angle of inclination relative to a vertical extending from a top surface of the MOS substrate.

Abstract: Embodiments of the present disclosure generally relate to the fabrication of integrated circuits and to apparatus for use within a substrate processing chamber to improve film thickness uniformity. More specifically, the embodiments of the disclosure relate to an edge ring. The edge ring may include an overhang ring.

Abstract: Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode is disposed over the gate dielectric layer. The gate dielectric layer has a Dit of about 5e10 cm?2 eV?1 to about 5e11 cm?2 eV?1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.

Abstract: Apparatus and methods for modifying a susceptor having a silicon carbide (SiC) surface. The method includes exposing the silicon carbide surface (SiC) to an atmospheric plasma. The method increases the atomic oxygen content of the silicon carbide (SiC) surface. The disclosure also describes a plasma treatment apparatus having a susceptor holding assembly and a plasma nozzle.

Abstract: The disclosure describes a plasma source assemblies comprising a differential screw assembly, an RF hot electrode, a top cover, an upper housing and a lower housing. The differential screw assembly is configured to provide force to align the plasma source assembly vertically matching planarity of a susceptor. More particularly, the differential screw assembly increases a distance between the top cover and the upper housing to align the gap with the susceptor. The disclosure also provides a better thermal management by cooling fins. A temperature capacity of the plasma source assemblies is extended by using titanium electrode. The disclosure provides a cladding material covering a portion of a first surface of RF hot electrode, a second surface of RF hot electrode, a bottom surface of RF hot electrode, a portion of a surface of the showerhead and a portion of lower housing surface.

Abstract: An apparatus with a grating structure and a method for forming the same are disclosed. The grating structure includes forming a wedge-shaped structure in a grating layer using a grayscale resist and photo lithography. A plurality of channels is formed in the grating layer to define slanted grating structures therein. The wedge-shaped structure and the slanted grating structures are formed using a selective etch process.

Abstract: Methods for plasma enhanced atomic layer deposition (PEALD) of low-K films are described. A method of depositing a film comprises exposing a substrate to a silicon precursor having the general formula (I) wherein R1, R2, R3, R4, R5, and R6 are independently selected from hydrogen (H), substituted alkyl, or unsubstituted alkyl; purging the processing chamber of the silicon precursor; exposing the substrate to a carbon monoxide (CO) plasma to form one or more of a silicon oxycarbide (SiOC) or silicon oxycarbonitride (SiOCN) film on the substrate; and purging the processing chamber.

Abstract: A method includes receiving one or more parameters associated with a plurality of metal plates. The method further includes determining, based on the one or more parameters, a plurality of predicted deformation values associated with the plurality of metal plates. Each of the plurality of predicted deformation values correspond to a corresponding metal plate of the plurality of metal plates. The method further includes causing, based on the plurality of predicted deformation values, the plurality of metal plates to be diffusion bonded to produce a bonded metal plate structure.

Abstract: Disclosed herein are systems and methods for polishing internal surfaces of apertures in semiconductor processing chamber components. A method includes providing a ceramic article having at least one aperture, the ceramic article being a component for a semiconductor processing chamber. The method further includes polishing the at least one aperture based on flowing an abrasive media through the at least one aperture of the ceramic article, the abrasive media including a polymer base and a plurality of abrasive particles.