Abstract: Provided are self-aligned double patterning methods including feature trimming. The SADP process is performed in a single batch processing chamber in which the substrate is laterally moved between sections of the processing chamber separated by gas curtains so that each section independently has a process condition.

Abstract: Apparatus and method for removing material from the susceptor of a batch processing chamber are described. The apparatus comprises a polishing tool including a rotatable platen positioned above the susceptor. A method comprises contacting material deposited on the susceptor with the rotatable platen to remove the material from the susceptor.

Abstract: Examples of the present technology include processing methods to incorporate stress in a channel region of a semiconductor transistor. The methods may include depositing a stressed material on an adjacent layer, where the adjacent layer is disposed between the stressed material and semiconductor material having an incorporated dopant. The adjacent layer may be characterized by an increased stress level after the deposition of the stressed material. The method may further include heating the stressed material and the adjacent layer, and removing the stressed material from the adjacent layer. The adjacent layer retains at least a portion of the increased stress after the removal of the stressed material. Examples of the present technology also include semiconductor structures having a conductive layer with first stress, and an intermediate layer with second stress in contact with the conductive layer. The second tensile stress may be at least ten times the first tensile stress.

Abstract: Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating non-replacement word lines and replacement insulators. A filled slit extends through the memory stack, and there are at least two select gate for drain (SGD) isolation regions in the memory stack adjacent the filled slit. A select-gate-for-drain (SGD) cut is patterned into the top few pairs of alternating layers in the memory stacks. Through the cut opening, the sacrificial layer of the memory stacks is removed, and an insulator layer is used to fill the opening.

Abstract: A selector device for a memory cell in a memory array may include a first electrode, and a separator that include a first region of a single-composition layer of a mixed ionic-electronic conduction material with a first concentration of defects; and a second region of a single-composition layer of a transitional metal oxide with a second concentration of defects that is different from the first concentration of defects. The selector device may also include a second electrode, where the separator is between the first electrode and the second electrode.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for obtaining a fluorescence microscope image that depicts a sample and a plurality of fiducial markers, identifying the plurality of fiducial markers in the image, and using the plurality of fiducial markers to register the image. The sample and the plurality of fiducial markers have a common fluorescence color, and identifying the plurality of fiducial markers in the image includes comparing a spatial intensity distribution of a plurality of fluorescent regions of the image to a reference distribution function.

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.

Abstract: A semiconductor processing system may include a substrate pedestal. The system may also include at least one fluid channel having a delivery portion configured to deliver a temperature controlled fluid to the substrate pedestal, and having a return portion configured to return the temperature controlled fluid from the substrate pedestal. The system may also include a heater coupled with the delivery portion of the at least one fluid channel. The system may also include a temperature measurement device coupled with the return portion of the at least one fluid channel, and the temperature measurement device may be communicatively coupled with the heater.

Abstract: Embodiments include a real time etch rate sensor and methods of for using a real time etch rate sensor. In an embodiment, the real time etch rate sensor includes a resonant system and a conductive housing. The resonant system may include a resonating body, a first electrode formed over a first surface of the resonating body, a second electrode formed over a second surface of the resonating body, and a sacrificial layer formed over the first electrode. In an embodiment, at least a portion of the first electrode is not covered by the sacrificial layer. In an embodiment, the conductive housing may secure the resonant system. Additionally, the conductive housing contacts the first electrode, and at least a portion of an interior edge of the conductive housing may be spaced away from the sacrificial layer.

Abstract: A method of encapsulating an organic light-emitting diode display includes depositing a plurality of first polymer projections onto a light-emitting side of a display layer having a plurality of organic light-emitting diodes (OLEDs) such that the plurality of first polymer projections have spaces therebetween that expose an underlying surface, and conformally coating the first polymer projections and the spaces between the first polymer projections with a first dielectric layer such that the first dielectric layer has side walls along sides of the first polymer projections and defines wells in spaces between the side walls.

Abstract: A method for forming microvias for packaging applications is disclosed. A sacrificial photosensitive material is developed to form microvias with reduced diameter and improved placement accuracy. The microvias are filled with a conductive material and the surrounding dielectric is removed and replaced with an RDL polymer layer.

Abstract: Gas distribution modules comprising a housing with an upper plenum and a lower plenum are described. One of the upper plenum and lower plenum is in fluid communication with an inlet and the other is in fluid communication with an outlet. A plurality of upper passages connects the upper plenum to the bottom of the housing to allow a flow of gas to pass through and be isolated from the first plenum.

Abstract: Gas injector inserts having a wedge-shaped housing, at least one first slot and at least one second slot are described. The housing has a first opening in the back face that is in fluid communication with the first slot in the front face and a second opening in the back face that is in fluid communication with the second slot in the front face. Each of the first slot and the second slot has an elongate axis that extends from the inner peripheral end to the outer peripheral end of the housing. The gas injector insert is configured to provide a flow of gas through the first slots at supersonic velocity. Gas distribution assemblies and processing chambers including the gas injector inserts are described.

Abstract: Methods of producing a self-aligned structure comprising a metal chalcogenide are described. Some methods comprise forming a metal-containing film in a substrate feature and exposing the metal-containing film to a chalogen precursor to form a self-aligned structure comprising a metal chalcogenide. Some methods comprise forming a metal-containing film in a substrate feature, expanding the metal-containing film to form a pillar and exposing the pillar to a chalogen precursor to form a self-aligned structure comprising a metal chalcogenide. Some methods comprise directly forming a metal chalcogenide pillar in a substrate feature to form a self-aligned structure comprising a metal chalcogenide. Methods of forming self-aligned vias are also described.

Abstract: Methods of depositing a metal film by exposing a substrate surface to a halide precursor and an organosilane reactant are described. The halide precursor comprises a compound of general formula (I): MQzRm, wherein M is a metal, Q is a halogen selected from Cl, Br, F or I, z is from 1 to 6, R is selected from alkyl, CO, and cyclopentadienyl, and m is from 0 to 6. The aluminum reactant comprises a compound of general formula (II) or general formula (III): wherein R1, R2, R3, R4, R5, R6, R7, R8, Ra, Rb, Rc, Rd, Re, and Rf are independently selected from hydrogen (H), substituted alkyl or unsubstituted alkyl; and X, Y, X?, and Y? are independently selected from nitrogen (N) and carbon (C).

Abstract: Nanopore flow cells and methods of manufacturing thereof are provided herein. In one embodiment a method of forming a flow cell includes forming a multi-layer stack on a first substrate, e.g., a monocrystalline silicon substrate, before transferring the multi-layer stack to a second substrate, e.g., a glass substrate. Here, the multi-layer stack features a membrane layer, having a first opening formed therethrough, where the membrane layer is disposed on the first substrate, and a material layer is disposed on the membrane layer. The method further includes patterning the second substrate to form a second opening therein and bonding the patterned surface of the second substrate to a surface of the multi-layer stack. The method further includes thinning the first substrate and thinning the second substrate. Here, the second substrate is thinned to where the second opening is disposed therethrough.

Abstract: A system for extending the life of a repeller in an IHC ion source is disclosed. The system includes an IHC ion source wherein the back surface of the repeller has been shaped to reduce the possibility of electrical shorts. The separation distance between the back surface of the repeller and the chamber wall behind the repeller is increased along its outer edge, as compared to the separation distance near the center of the repeller. This separation distance reduces the possibility that deposited material will flake and short the repeller to the chamber wall. Further, in certain embodiments, the separation distance between the back surface of the repeller and the chamber wall near the center of the repeller is unchanged, so as to minimize the flow of gas that exits from the chamber. The back surface of the repeller may be tapered, stepped or arced to achieve these criteria.

Abstract: Embodiments generally relate to a chamber component to be used in plasma processing chambers for semiconductor or display processing. In one embodiment, a chamber component includes a textured surface having a surface roughness ranging from about 150 microinches to about 450 microinches and a coating layer disposed on the textured surface. The coating layer may be a silicon layer having a purity ranging from about 90 weight percent to about 99 weight percent, a thickness ranging from about 50 microns to about 500 microns, and an electrical resistivity ranging from about 1 E-3 ohm*m to about 1 E3 ohm*m. The coating layer provides strong adhesion for materials deposited in the plasma processing chamber, which reduces the materials peeling from the chamber component. The coating layer also enables oxygen plasma cleaning for further reducing materials deposited on the chamber component and provides the protection of the textured surface located therebelow.

Abstract: An apparatus for positioning micro-devices on a substrate includes one or more supports to hold a donor substrate and a destination substrate, an adhesive dispenser to deliver adhesive on micro-devices on the donor substrate, a transfer device including a transfer surface to transfer the micro-devices from the donor substrate to the destination substrate, and a controller. The controller is configured to operate the adhesive dispenser to selectively dispense the adhesive onto selected micro-devices on the donor substrate based on a desired spacing of the selected micro-devices on the destination substrate. The controller is configured to operate the transfer device such that the transfer surface engages the adhesive on the donor substrate to cause the selected micro-devices to adhere to the transfer surface and the transfer surface then transfers the selected micro-devices from the donor substrate to the destination substrate.

Abstract: Implementations described herein provide a pedestal lift assembly for a plasma processing chamber and a method for using the same. The pedestal lift assembly has a platen configured to couple a shaft of a pedestal disposed in the plasma processing chamber. An absolute linear encoder is coupled to a fixed frame wherein the absolute linear encoder is configured to detect incremental movement of the platen. A lift rod is attached to the platen. A motor rotor encoder brake module (MRBEM) is coupled to the fixed frame and moveably coupled to the lift rod, the motor encoder brake module configured to move the lift rod in a first direction and a second direction, wherein the movement of the lift rod results in the platen traveling vertically relative to the fixed frame.