Abstract: A plasma reactor includes a chamber body having an interior space that provides a plasma chamber, a gas distribution port to deliver a processing gas to the plasma chamber, a workpiece support to hold a workpiece, an antenna array comprising a plurality of monopole antennas extending partially into the plasma chamber, and an AC power source to supply a first AC power to the plurality of monopole antennas.

Abstract: A beamline ion implanter and a method of operating a beamline ion implanter. A method may include performing an ion implantation procedure during a first time period on a first set of substrates, in a process chamber of the ion implanter, and performing a first pressure-control routine during a second time period by: introducing a predetermined gas to reach a predetermined pressure into at least a downstream portion of the beam-line for a second time period. The method may include, after completion of the first pressure-control routine, performing the ion implantation procedure on a second set of substrates during a third time period.

Abstract: An ion implantation system, including an ion source and extraction system, arranged to generate an ion beam at a first energy, and a linear accelerator, disposed downstream of the ion source, the linear accelerator arranged to receive the ion beam as a bunched ion beam accelerate the ion beam to a second energy, greater than the first energy. The linear accelerator may include a plurality of acceleration stages, wherein a given acceleration stage of the plurality of acceleration stages comprises: a drift tube assembly, arranged to conduct the ion beam; a resonator, electrically coupled to the drift tube assembly; and an RF power assembly, coupled to the resonator, and arranged to output an RF signal to the resonator. As such, the given acceleration stage does not include a quadrupole element.

Abstract: Provided are methods of depositing a film in high aspect ratio (AR) structures with small dimensions. The method provides flowable deposition for seamless gap-fill, film densification by low temperature inductively coupled plasma (ICP) treatment (<600° C.), optional film curing, and etch back to form a low-k dielectric film having a dielectric constant, k-value less than 3.

Abstract: A deposition system, and a method of operation thereof, includes: a cathode; a shroud below the cathode; a rotating shield below the cathode for exposing the cathode through the shroud and through a shield hole of the rotating shield; and a rotating pedestal for producing a material to form a carrier over the rotating pedestal, wherein the material having a non-uniformity constraint of less than 1% of a thickness of the material and the cathode having an angle between the cathode and the carrier.

Abstract: Horizontal gate-all-around devices and methods of manufacturing the same are described. The hGAA devices comprise an oxidize layer on a semiconductor material between source regions and drain regions of the device. The method includes radical plasma oxidation (RPO) of semiconductor material layers between source regions and drain regions of an electronic device.

Abstract: A method of fabricating a multi-color display includes dispensing a photo-curable fluid over a display having an array of LEDs disposed below a cover layer. The cover has an outer surface with a plurality of recesses, and the photo-curable fluid fills the recesses. The photo-curable fluid includes a color conversion agent. A plurality of LEDs in the array are activated to illuminate and cure the photo-curable fluid to form a color conversion layer in the recesses over the activated LEDs. This layer will convert light from these LEDs to light of a first color. An uncured remainder of the photo-curable fluid is removed. Then the process is repeated with a different photo-curable fluid having a different color conversion agent and a different plurality of LEDs. This forms a second color conversion layer in different plurality of recesses to convert light from these LEDs to light of a second color.

Abstract: Embodiments of the present disclosure relate to methods for positioning masks in a propagation direction of a light source. The masks correspond to a pattern to be written into a photoresist layer of a substrate. The masks are positioned by stitching a first mask and a second mask. The first mask includes a set of first features having first feature extensions extending therefrom at first feature interfaces. The second mask includes a set of second features having second feature extensions extending therefrom at second feature interfaces. Each first feature extension stitches with each corresponding second feature extension to form each stitched portion of a first stitched portion of the first pair of masks. The stitched portion of the first pair of masks defines a portion of the pattern to be written into the photoresist layer.

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.

Abstract: Embodiments described herein relate to substrate processing methods. More specifically, embodiments of the disclosure provide for an MRAM back end of the line integration process which utilizes a zero mark for improved patterning alignment. In one embodiment, the method includes fabricating a substrate having at least a bottom contact and a via extending from the bottom contact in a first region and etching a zero mark in the substrate in a second region apart from the first region. The method also includes depositing a touch layer over the substrate in the first region and the second region, depositing a memory stack over the touch layer in the first region and the second region, and depositing a hardmask over the memory stack layer in the first region and the second region.

Abstract: Embodiments of the present disclosure provide protective coatings, i.e., diffusion and thermal barrier coatings, for aluminum alloy substrates. In particular, embodiments described herein provide a protective layer stack comprising a tantalum nitride layer disposed on an aluminum alloy substrate and a ceramic layer disposed on the tantalum nitride layer. In some embodiments, the aluminum alloy substrates comprise processing chambers and processing chamber components used in the field of electronic device manufacturing, e.g., semiconductor device manufacturing. In one embodiment, an article includes a substrate, a tantalum nitride layer disposed on the substrate, and a ceramic layer disposed on the tantalum nitride layer.

Abstract: An ion source having a thermally isolated repeller is disclosed. The repeller comprises a repeller disk and a plurality of spokes originating at the back surface of the repeller disk and terminating in a post. In certain embodiments, the post may be hollow through at least a portion of its length. The use of spokes rather than a central stem may reduce the thermal conduction from the repeller disk to the post. By incorporating a hollow post, the thermal conduction is further reduced. This configuration may increase the temperature of the repeller disk by more than 100° C. In certain embodiments, radiation shields are provided on the back surface of the repeller disk to reduce the amount of radiation emitted from the sides of the repeller disk. This may also help increase the temperature of the repeller. A similar design may be utilized for other electrodes in the ion source.

Abstract: A deposition system and a method of operation thereof are disclosed. A PVD chamber is disclosed comprising a plurality of cathode assemblies, a rotating shield below the plurality of cathode assemblies to expose one of the plurality cathode assemblies through the shroud and through a shield hole of the shield, the shield comprising a top surface including a raised peripheral frame. A shield mount sized and shaped to engage with the raised peripheral frame to secure the shield mount to the shield.

Abstract: A semiconductor processing chamber may include a remote plasma region, and a processing region fluidly coupled with the remote plasma region. The processing region may be configured to house a substrate on a support pedestal. The support pedestal may include a first material at an interior region of the pedestal. The support pedestal may also include an annular member coupled with a distal portion of the pedestal or at an exterior region of the pedestal. The annular member may include a second material different from the first material.

Abstract: Apparatus and methods to control the phase of power sources for plasma process regions in a batch process chamber. A master exciter controls the phase of the power sources during the process sequence based on feedback from the match circuits of the respective plasma sources.

Abstract: Exemplary processing methods may include forming a first deposition plasma of a silicon-and-nitrogen-containing precursor. The methods may include depositing a first portion of a silicon nitride material on a semiconductor substrate with the first deposition plasma. A first treatment plasma of a helium-and-nitrogen-containing precursor may be formed to treat the first portion of the silicon nitride material with the first treatment plasma. A second deposition plasma may deposit a second portion of a silicon nitride material, and a second treatment plasma may treat the second portion of the silicon nitride material. A flow rate ratio of helium-to-nitrogen in the first treatment plasma may be lower than a He/N2 flow rate ratio in the second treatment plasma. A first power level from a plasma power source that forms the first treatment plasma may be lower than a second power level that forms the second treatment plasma.

Abstract: The present technology encompasses plasma sources including a first plate defining a first plurality of apertures arranged in a first set of rows. The first plate may include a first set of electrodes extending along a separate row of the first set of rows. The plasma sources may include a second plate defining a second plurality of apertures arranged in a second set of rows. The second plate may include a second set of electrodes extending along a separate row of the second set of rows. Each aperture of the second plurality of apertures may be axially aligned with an aperture of the first plurality of apertures. The plasma sources may include a third plate positioned between the first plate and the second plate. The third plate may define a third plurality of apertures.

Abstract: Describes are shutter disks comprising one or more of titanium (Ti), barium (Ba), or cerium (Ce) for physical vapor deposition (PVD) that allows pasting to minimize outgassing and control defects during etching of a substrate. The shutter disks incorporate getter materials that are highly selective to reactive gas molecules, including O2, CO, CO2, and water.

Abstract: Apparatuses and methods to provide electronic devices having metal films are provided. Some embodiments of the disclosure utilize a metallic tungsten layer as a liner that is filled with a metal film comprising cobalt. The metallic tungsten layer has good adhesion to the cobalt leading to enhanced cobalt gap-fill performance.

Abstract: Exemplary processing methods may include flowing a first deposition precursor into a substrate processing region to form a first portion of an initial compound layer. The first deposition precursor may include an aldehyde reactive group. The methods may include removing a first deposition effluent including the first deposition precursor from the substrate processing region. The methods may include flowing a second deposition precursor into the substrate processing region. The second deposition precursor may include an amine reactive group, and the amine reactive group may react with the aldehyde reactive group to form a second portion of the initial compound layer. The methods may include removing a second deposition effluent including the second deposition precursor from the substrate processing region. The methods may include annealing the initial compound layer to form an annealed carbon-containing material on the surface of the substrate.