Abstract: A method for inspecting a three dimensional structure of a microscopic scale of a sample, the method may include obtaining an image of the three dimensional structure; obtaining a reference image of a reference three dimensional structure, the reference three dimensional structure and the three dimensional structure are ideally identical to each other; wherein each one of the image and the reference image was generated using optics that includes a phase mask, wherein the phase mask virtually expands a depth of field of the optics by encoding depth information over a depth range that exceeds the depth of field; generating a difference image that represents a difference between the image and the reference image; determining, based on the difference image, whether there is at least one defect in the three dimensional structure; wherein when determining that there is the at least one defect then providing a depth of the at least one defect.

Abstract: A method of forming a radio frequency (RF) strap for use in a process chamber is provided. The method includes positioning a core strap including a first material that is electrically and thermally conductive in a first electrochemical bath. The first electrochemical bath includes a first solvent and a first plating precursor. The method further includes forming a first protective coating on an outer surface of the core strap, removing the first solvent and the first plating precursor from the core strap having the first protective coating formed thereon, post-treating the core strap having the first protective coating formed thereon, positioning the core strap having the first protective coating formed thereon in a second electrochemical bath, and forming a second protective coating on an outer surface of the first protective coating.

Abstract: Exemplary semiconductor processing chambers may include a pedestal comprising a platen configured to support a semiconductor substrate across a surface of the platen. The chambers may include a first conductive mesh incorporated within the platen and configured to operate as a first chucking mesh. The first conductive mesh may extend radially across the platen. The chambers may include a second conductive mesh incorporated within the platen and configured to operate as a second chucking mesh. The second conductive mesh may be characterized by an annular shape. The second conductive mesh may be disposed between the first conductive mesh and the surface of the platen.

Abstract: Embodiments of the present disclosure generally relate to a substrate processing chamber, and components thereof, for forming semiconductor devices. The processing chamber comprises a substrate support, and an edge ring is disposed around the substrate support. The edge ring comprises a material selected from the group consisting of quartz, silicon, cross-linked polystyrene and divinylbenzene, polyether ether ketone, Al2O3, and AlN. The material of the edge ring is selected to modulate the properties of hardmask films deposited on substrates in the processing chamber. As such, hardmask films having desired film properties can be deposited in the processing chamber without scaling up the RF power to the chamber.

Abstract: Processing methods may be performed to produce semiconductor structures that may include a high-k dielectric material. The methods may include forming a silicon layer over a semiconductor substrate. The semiconductor substrate may include silicon germanium. The methods may include oxidizing a portion of the silicon layer to form a sacrificial oxide while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The methods may include removing the sacrificial oxide. The methods may include oxidizing the portion of the silicon layer in contact with the semiconductor substrate to form an oxygen-containing material. The methods may include forming a high-k dielectric material overlying the oxygen-containing material.

Abstract: Described are methods for doping barrier layers such as tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), niobium (Nb), niobium nitride (NbN), manganese (Mn), manganese nitride (MnN), titanium (Ti), titanium nitride (TiN), molybdenum (Mo), and molybdenum nitride (MoN), and the like. Dopants may include one or more of one or more of ruthenium (Ru), manganese (Mn), niobium (Nb), cobalt (Co), vanadium (V), copper (Cu), aluminum (Al), carbon (C), oxygen (O), silicon (Si), molybdenum (Mo), and the like. The doped barrier layer provides improved adhesion at a thickness of less than about 15 ?.

Abstract: A gas injection apparatus for a thermal processing chamber includes a gas injector having an inlet at a first end and a port at a second end; and a plate having a first opening matching the port, one or more second openings, and at least one circuitous flow path defined by the plate and fluidly connecting the first opening to the one or more second openings.

Abstract: Disclosed herein are approaches for adjusting extraction slits of an extraction plate using a set of adjustable beam blockers. In one approach, an ion extraction optics may include an extraction plate including a first opening and a second opening, and a first beam blocker extending over the first opening and a second beam blocker extending over the second opening. Each of the first and second beam blockers may include an inner slit defined by a first distance between an inner edge and the extraction plate, and an outer slit defined by a second distance between an outer edge and the extraction plate, wherein the first and second beam blockers are movable to vary at least one of the first distance and the second distance. As a result, extraction through the inner and outer slits of ion beamlets characterized by similar mean angles may be achieved.

Abstract: Electronic devices and methods to form electronic devices having a self-aligned via are described. An adhesion enhancement layer is utilized to promote adhesion between the conductive material and the sidewalls of the at least one via opening. The self-aligned vias decrease via resistance and reduce the potential to short to the wrong metal line.

Abstract: A method, an inspection system and a sensing unit. The sensing unit may include a light recycling optics and a photon to electron converter. The photon to electron converter is configured to receive a first light beam emitted from the object and impinging on the partially reflective surface at a first oblique angle, absorb a first portion and reflect a second portion of the first light beam to provide a first reflected beam. The light recycling optics is configured to redirect, towards the partially reflective surface, one or more reflected beams reflected from the partially reflective surface to provide one or more recycled beams. The photon to electron converter is configured to output electrons that represents an absorbed portion of the input light beam and an absorbed portion of each one of the one or more recycled beam.

Abstract: A ferroelectric capacitor or a ferroelectric transistor may include a first metal layer having a first metal having a first work function, and a second metal layer having a second metal having a second work function. The capacitor may also include a a vertical electrode and a ferroelectric material that surrounds the vertical electrode and forms a plurality of switching regions in the ferroelectric material. The transistor may include a vertical channel, a vertical buffer layer that surround the vertical channel, and a ferroelectric material that surrounds the vertical buffer layer and forms a plurality of gate regions in the ferroelectric material.

Abstract: A heater assembly having a top seal and a second seal configured to account for deviation in processing heights and motor runoff of a heater standoff. The top seal is positioned between a shield plate and a top plate and the bottom seal is positioned between a heater mounting base and the heater standoff.

Abstract: Process chambers and methods for calibrating components of a processing chamber while the chamber volume is under vacuum are described. The process chamber includes a motor shaft connected to the process chamber with a plurality of motor bolts. A support plate is positioned under the chamber floor to accommodate for deflection of the chamber floor due to vacuum conditions within the chamber volume. A bellows assembly extending from the chamber floor to the support plate maintains vacuum conditions within the chamber.

Abstract: Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.

Abstract: Methods to manufacture integrated circuits are described. Nanocrystalline diamond is used as a hard mask in place of amorphous carbon. Provided is a method of processing a substrate in which nanocrystalline diamond is used as a hard mask, wherein processing methods result in a smooth surface. The method involves two processing parts. Two separate nanocrystalline diamond recipes are combined—the first and second recipes are cycled to achieve a nanocrystalline diamond hard mask having high hardness, high modulus, and a smooth surface. In other embodiments, the first recipe is followed by an inert gas plasma smoothening process and then the first recipe is cycled to achieve a high hardness, a high modulus, and a smooth surface.

Abstract: Exemplary methods of semiconductor processing may include flowing a silicon-containing precursor, a nitrogen-containing precursor, and diatomic hydrogen into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber. The methods may also include forming a plasma of the silicon-containing precursor, the nitrogen-containing precursor, and the diatomic hydrogen. The plasma may be formed at a frequency above 15 MHz. The methods may also include depositing a silicon nitride material on the substrate.

Abstract: Methods for forming circuit boards and circuit boards using an adhesion layer are described. A substrate with two surfaces is exposed to a bifunctional organic compound to form an adhesion layer on the first substrate surface. A resin layer is then deposited on the adhesion layer and the exposed substrate surfaces. Portions of the resin layer may be removed to expose metal pads for contacts.

Abstract: A device may include a first electrode, a barrier layer, and a tunneling layer having a first dielectric constant. The barrier layer may be between the first electrode and the tunneling layer. The device may also include an active layer having a second dielectric constant. The tunneling layer may be between the first electrode and the active layer. The device may further include a second electrode. The active layer may be between the tunneling layer and the second electrode.

Abstract: In one embodiment, a method may include providing a substrate, comprising a plurality of surface features, an isolation layer, disposed between the plurality of surface features, and a substrate base, disposed subjacent the isolation layer and the plurality of surface features, wherein the plurality of surface features extend above a surface of the isolation layer. The method may include directing a low energy ion beam to the substrate, when the substrate is heated at a targeted temperature, wherein an altered layer is formed within an outer portion of the isolation layer, and wherein an inner portion of the isolation layer is not implanted.

Abstract: In one embodiment, a method of selectively forming a deposit may include providing a substrate, the substrate having a plurality of surface features, extending at a non-zero angle of inclination with respect to a perpendicular to a plane of the substrate. The method may include directing a reactive beam to the plurality of surface features, the reactive beam defining a non-zero angle of incidence with respect to a perpendicular to the plane of the substrate, wherein a seed layer is deposited on a first portion of the surface features, and is not deposited on a second portion of the surface features. The method may further include exposing the substrate to a reactive deposition process after the directing the reactive ion beam, wherein a deposit layer selectively grows over the seed layer.