Abstract: Provided is a processing chamber configured to contain a semiconductor substrate in a processing region of the chamber. The processing chamber includes a remote plasma unit and a direct plasma unit, wherein one of the remote plasma unit or the direct plasma unit generates a remote plasma and the other of the remote plasma unit or the direct plasma unit generates a direct plasma. The combination of a remote plasma unit and a direct plasma unit is used to remove, etch, clean, or treat residue on a substrate from previous processing and/or from native oxide formation. The combination of a remote plasma unit and direct plasma unit is used to deposit thin films on a substrate.

Abstract: Exemplary semiconductor processing chambers may include a gasbox. The chambers may include a substrate support. The chambers may include a blocker plate positioned between the gasbox and the substrate support. The blocker plate may define a plurality of apertures through the plate. The chambers may include a faceplate positioned between the blocker plate and substrate support. The faceplate may be characterized by a first surface facing the blocker plate and a second surface opposite the first surface. The second surface of the faceplate and the substrate support may at least partially define a processing region within the semiconductor processing chamber. The faceplate may be characterized by a central axis, and the faceplate may define a plurality of apertures through the faceplate. The faceplate may define a central recess about the central axis extending from the second surface of the faceplate to a depth less than a thickness of the faceplate.

Abstract: Exemplary semiconductor processing chambers may include a gasbox characterized by a first surface and a second surface opposite the first surface. The gasbox may define a central aperture. The gasbox may define an annular channel extending about the central aperture. The annular channel may be fluidly accessible from the first surface of the gasbox. The gasbox may further define a plurality of outlet apertures extending from the annular channel through the second surface of the gasbox.

Abstract: Exemplary deposition methods may include forming a plasma of an oxygen-containing precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include, while maintaining the plasma of the oxygen-containing precursor, flowing a silicon-containing precursor into the processing region of the semiconductor processing chamber at a first flow rate. The methods may include ramping the first flow rate of the silicon-containing precursor over a period of time to a second flow rate greater than the first flow rate. The methods may include depositing a silicon-containing material on the semiconductor substrate.

Abstract: Described are methods for controlling the doping of metal nitride films such as TaN, TiN and MnN. The temperature during deposition of the metal nitride film may be controlled to provide a film density that permits a desired amount of doping. Dopants may include Ru, Cu, Co, Mn, Mo, Al, Mg, Cr, Nb, Ta, Ti and V. The metal nitride film may optionally be exposed to plasma treatment after doping.

Abstract: Embodiments of the present technology may include an electrostatic chuck. The chuck may include a top surface, defining a recessed portion of the chuck. The recessed portion of the chuck may be configured to support a substrate. The chuck may further include a first electrode and a second electrode. The first electrode and the second electrode may be disposed within the chuck. The first electrode and the second electrode may be substantially coplanar. In addition, the chuck may include a third electrode. The third electrode may be disposed within the chuck. Furthermore, the third electrode may have an annular shape. The third electrode may be separated from the first electrode and the second electrode. In addition, the third electrode may be substantially parallel to the first electrode and the second electrode. Systems and methods including the electrostatic chuck are also described.

Abstract: Methods for pre-cleaning substrates having metal and dielectric surfaces are described. A substrate comprising a surface structure with a metal bottom, dielectric sidewalls, and a field of dielectric is exposed to a dual plasma treatment in a processing chamber to remove chemical residual and/or impurities from the metal bottom, the dielectric sidewalls, and/or the field of the dielectric and/or repair surface defects in the dielectric sidewalls and/or the field of the dielectric. The dual plasma treatment comprises a direct plasma and a remote plasma.

Abstract: Embodiments disclosed herein include photodiodes and methods of forming such photodiodes. In an embodiment, a method of creating a photodiode, comprises disposing an absorber layer over a first contact, wherein the absorber layer comprises a first conductivity type, and disposing a semiconductor layer over the absorber, wherein the semiconductor layer has a second conductivity type that is opposite from the first conductivity type. In an embodiment, the method further comprises disposing a hole blocking layer over the semiconductor layer, wherein the hole blocking layer is formed with a reactive sputtering process with a processing gas that comprises oxygen, and disposing a second contact over the hole blocking layer.

Abstract: Certain aspects of the present disclosure provide techniques for automatically detecting and classifying tumor regions in a tissue slide. The method generally includes obtaining a digitized tissue slide from a tissue slide database and determining, based on output from a tissue classification module, a type of tissue of shown in the digitized tissue slide. The method further includes determining, based on output from a tumor classification model for the type of tissue, a region of interest (ROI) of the digitized tissue slide and generating a classified slide showing the ROI of the digitized tissue slide and an estimated diameter of the ROI. The method further includes displaying on an image display unit, the classified slide and user interface (UI) elements enabling a pathologist to enter input related to the classified slide.

Abstract: A method for setting memory elements in a plurality of states includes applying a set signal to a memory element to transition the memory element from a low-current state to a high-current state; applying a partial reset signal to the memory element to transition the memory element from the high-current state to a state between the high-current state and the low-current state; determining whether the state corresponds to a predetermined state; and applying one or more additional partial reset signals to the memory element until the state corresponds to the predetermined current state. The memory element may be coupled in series with a transistor, and a voltage control circuit may apply voltages to the transistor to set and partially reset the memory element.

Abstract: Embodiments presented herein provide techniques for executing a block-based (BB) workflow to solve a constraint programming (CP) model related to a semiconductor manufacturing environment. Embodiments include receiving at least one BB workflow comprising a plurality of blocks. The plurality of blocks may specify a set of operations. Embodiments include accessing a plurality of block definitions corresponding to the plurality of blocks. Embodiments include executing the at least one BB workflow by performing the set of operations based on the plurality of block definitions, including extracting data from the semiconductor manufacturing environment, the data comprising both static data and dynamic data related to equipment in the manufacturing environment, creating the CP model based on the data and at least one constraint defined in the BB workflow, using a solver to determine a solution to the CP model; and publishing the solution to at least one component in the semiconductor manufacturing environment.

Abstract: Methods, apparatus, and assemblies are provided for a substrate carrier adapter insert including an adapter frame including a support rail adapted to support one or more substrates in a substrate carrier, a frame extension coupled to, or integral with, the adapter frame, and a mapping feature formed on the frame extension and disposed to be detected by a sensor for determining whether an adapter insert is present or absent in a substrate carrier. Numerous additional features are disclosed.

Abstract: Gas injector units for processing chambers having one or more of scavenging ports, differential pressure ports and variable surfaces for variable injector to substrate gap distances are described. Gas distribution assemblies and processing chambers incorporating the gas injector units are also described.

Abstract: Implementations of the present disclosure include methods and apparatuses utilized to reduce particle generation within a processing chamber. In one implementation, a lid for a substrate processing chamber is provided. The lid includes a cover member having a first surface and a second surface opposite the first surface, a central opening through the cover member, wherein an inner profile of the central opening includes a first section having a first diameter, a second section having a second diameter, and a third section having a third diameter, wherein the second diameter is between the first diameter and the third diameter, and the first diameter increases from the second section toward the first surface of the cover member, and a trench formed along a closed path in the first surface and having a recess formed in an inner surface of the trench.

Abstract: The present disclosure provide methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes forming a multi-material layer on a bottom structure on a substrate, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, selectively removing the second layer from the multi-material layer from the substrate, and selectively oxidizing the bottom structure on the substrate after removing the second layer from the multi-material layer.

Abstract: Disclosed embodiments generally relate to a processing chamber that includes a perforated lid, a gas blocker disposed on the perforated lid, and a substrate support disposed below the perforated lid. The gas blocker includes a gas manifold, a central gas channel formed in the gas manifold, a first gas distribution plate that includes inner and outer trenches surrounding the central gas channel, and a first and second gas channels formed in the gas manifold. The first gas channel is in fluid communication with a first gas source and the inner trench, and the second gas channel is in fluid communication with the first gas source and the outer trench and a second gas distribution plate The first gas channel is in further fluid communication with a third gas distribution plate that is disposed below the second gas distribution plate, and a plurality of pass-through channels that are disposed between the second gas distribution plate and the third gas distribution plate.

Abstract: A metrology system for obtaining a measurement representative of a thickness of a layer on a substrate includes a camera positioned to capture a color image of at least a portion of the substrate. A controller is configured to receive the color image from the camera, store a predetermined path in a coordinate space of at least two dimension including a first color channel and a second color channel, store a function that provides a value representative of a thickness as a function of a position on the predetermined path, determine a coordinate of a pixel in the coordinate space from color data in the color image for the pixel, determine a position of a point on the predetermined path that is closest to the coordinate of the pixel, and calculate a value representative of a thickness from the function and the position of the point on the predetermined path.

Abstract: A resistive random-access memory (ReRAM) device may include a thermally engineered layer that is positioned adjacent to an active layer and configured to act as a heat sink during filament formation in response to applied voltages. The thermally engineered layer may act as one of the electrodes on the ReRAM device and may be adjacent to any side of the active layer. The active layer may also include a plurality of individual active layers. Each of the active layers may be associated with a different dielectric constant, such that the middle active layer has a dielectric constant that is significantly higher than the other two surrounding active layers.

Abstract: A showerhead with an embedded nut is disclosed. The showerhead comprises an embedded nut within a cavity. The nut may be engaged by a bolt through an opening in the cavity to support the showerhead. The apparatus allows for the support of the showerhead without the potential for metal contamination.

Abstract: Embodiments disclosed herein relate to methods for forming memory devices, and more specifically to improved methods for forming a dielectric encapsulation layer over a memory material in a memory device. In one embodiment, the method includes thermally depositing a first material over a memory material at a temperature less than the temperature of the thermal budget of the memory material, exposing the first material to nitrogen plasma to incorporate nitrogen in the first material, and repeating the thermal deposition and nitrogen plasma operations to form a hermetic, conformal dielectric encapsulation layer over the memory material. Thus, a memory device having a hermetic, conformal dielectric encapsulation layer over the memory material is formed.