Abstract: Embodiments described herein relate to apparatus for measuring and characterizing performance of augmented and virtual reality waveguide structures utilizing glass substrates. The waveguide performance measuring systems generally include a light source configured to direct light towards an incoupling grating area on waveguide and one or more light detectors configured to collect light from an outcoupling grating area on a second side of the waveguide. The light source and one or more light detectors are disposed on one or more adjustable stages positioned about the waveguide. In certain embodiments, the one or more adjustable stages are configured to move in a linear fashion or revolve and/or rotate around the waveguide in an orbital motion.

Abstract: Provided are methods for the deposition of films comprising SiCN. Certain methods involve exposing a substrate surface to a silicon precursor, wherein the silicon precursor is halogenated with Cl, Br or I, and the silicon precursor comprises a halogenated silane, a halogenated carbosilane, an halogenated aminosilane or a halogenated carbo-sillyl amine. Then, the substrate surface can be exposed to a nitrogen-containing plasma or a nitrogen precursor and densification plasma.

Abstract: Methods for forming films during semiconductor device fabrication by soaking a substrate in dopant are discussed herein. The dopant soak is performed in a process chamber using at least one dopant precursor for a predetermined period of time to form a dopant layer on the substrate. The process chamber is subsequently purged of the at least one dopant precursor. At least one film precursor is introduced into the process chamber after the process chamber is purged. A film is epitaxially formed on the substrate to have at least one of a target resistivity, dopant concentration, and/or thickness. Post-processing operations can include annealing or patterning the semiconductor film, or depositing additional layers thereon.

Abstract: Implementations disclosed herein describe a bevel etch apparatus within a loadlock bevel etch chamber and methods of using the same. The bevel etch apparatus has a mask assembly within the loadlock bevel etch chamber. During an etch process, the mask assembly delivers a gas flow to control bevel etch without the use of a shadow frame. As such, the edge exclusion at the bevel edge can be reduced, thus increasing product yield.

Abstract: Electronic devices and methods to form electronic devices having a self-aligned via are described. An adhesion enhancement layer is utilized to promote adhesion between the conductive material and the sidewalls of the at least one via opening. The self-aligned vias decrease via resistance and reduce the potential to short to the wrong metal line.

Abstract: A method for forming a film of an oxide of In, Ga, and Zn, having a spinel crystalline phase comprises providing a substrate in a chamber; providing a sputtering target in said chamber, the target comprising an oxide of In, Ga, and Zn, wherein: In, Ga, and Zn represent together at least 95 at % of the elements other than oxygen, In represents from 0.6 to 44 at % of In, Ga, and Zn, Ga represents from 22 to 66 at % of In, Ga, and Zn, and Zn represents from 20 to 46 at % of In, Ga, and Zn; and forming a film on the substrate, the substrate being at a temperature of from 125° C. to 250° C., by sputtering the target with a sputtering gas comprising O2, the sputtering being performed at a sputtering power of at least 200 W.

Abstract: Methods for monitoring process chambers using a controllable plasma oxidation process followed by a controlled reduction process and metrology are described. In some embodiments, the metrology comprises measuring the reflectivity of the metal oxide film formed by the controllable plasma oxidation process and the reduced metal film or surface modified film formed by reducing the metal oxide film.

Abstract: An example semiconductor processing system may include a chamber body having sidewalls and a base. The processing system may also include a substrate support extending through the base of the chamber body. The substrate support may include a support platen configured to support a semiconductor substrate, and a shaft coupled with the support platen. The processing system may further include a plate coupled with the shaft of the substrate support. The plate may have an emissivity greater than 0.5. In some embodiments, the plate may include a radiation shied disposed proximate the support platen. In some embodiments, the plate may include a pumping plate disposed proximate the base of the chamber body. In some embodiments, the emissivity of the plate may range between about 0.5 and about 0.95.

Abstract: Plasma source assemblies comprising an RF hot electrode having a body and at least one return electrode spaced from the RF hot electrode to provide a gap in which a plasma can be formed. An RF feed is connected to the RF hot electrode at a distance from the inner peripheral end of the RF hot electrode that is less than or equal to about 25% of the length of the RF hot electrode.

Abstract: Exemplary methods of semiconductor processing may include depositing a material on a substrate seated on a substrate support housed in a processing region of a semiconductor processing chamber. The processing region may be at least partially defined by the substrate support and a faceplate. The substrate support may be at a first position within the processing region relative to the faceplate. The methods may include translating the substrate support to a second position relative to the faceplate. The methods may include forming a plasma of an etchant precursor within the processing region of the semiconductor processing chamber. The methods may include etching an edge region of the substrate.

Abstract: A graphene barrier layer is disclosed. Some embodiments relate to a graphene barrier layer capable of preventing diffusion from a fill layer into a substrate surface and/or vice versa. Some embodiments relate to a graphene barrier layer that prevents diffusion of fluorine from a tungsten layer into the underlying substrate. Additional embodiments relate to electronic devices which contain a graphene barrier layer.

Abstract: An exemplary system may include a chamber configured to contain a semiconductor substrate in a processing region of the chamber. The system may include a first remote plasma unit fluidly coupled with a first access of the chamber and configured to deliver a first precursor into the chamber through the first access. The system may still further include a second remote plasma unit fluidly coupled with a second access of the chamber and configured to deliver a second precursor into the chamber through the second access. The first and second access may be fluidly coupled with a mixing region of the chamber that is separate from and fluidly coupled with the processing region of the chamber. The mixing region may be configured to allow the first and second precursors to interact with each other externally from the processing region of the chamber.

Abstract: Embodiments of the present disclosure generally relate to apparatus and methods for semiconductor processing, more particularly, to a thermal process chamber. The thermal process chamber includes a substrate support, a first plurality of heating elements disposed over or below the substrate support, and a spot heating module disposed over the substrate support. The spot heating module is utilized to provide local heating of cold regions on a substrate disposed on the substrate support during processing. Localized heating of the substrate improves temperature profile, which in turn improves deposition uniformity.

Abstract: The present disclosure relate to methods and apparatus for temperature sensing and control during substrate processing. Substrate temperatures during processing, which are difficult to measure directly, may be determined by examination of deposited film properties or by measuring changes in power output over time of the substrate heating apparatus. Temperatures are determined for many substrates during processing, showing how substrate temperatures change over time, and the temperature changes are then used to build models via machine learning techniques. The models are used to adjust heating apparatus setpoints for future processing operations.

Abstract: Described herein are methods, apparatuses, and systems for reducing equipment repair time. Disclosed methods include collecting data including test substrate data or other metrology data and fault detection data for maintenance recovery of at least one manufacturing tool in a manufacturing facility. Disclosed methods include determining a relationship between tool parameter settings for the at least one manufacturing tool and at least some collected data including the test substrate data. The disclosure includes utilizing virtual metrology predictive algorithms and at least some collected data to obtain a metrology prediction and applying multivariate run-to-run (R2R) control modeling to obtain a tool parameter adjustment for at least one target parameter for the at least one manufacturing tool. The disclosure further includes applying the R2R control modeling to obtain tool parameter adjustments for at least one manufacturing tool.

Abstract: Embodiments include wafer and photomask processing equipment. An etch processing system including an endpoint detection system having a light source and a photodetector is described. In an example, the light source emits light toward an alignment region over a substrate support member of an etch chamber, and the photodetector receives a reflection of the light from the alignment region. The reflection is monitored for endpoint and process control. A second light source emits light toward the alignment region, and a camera receives the light to image the alignment region. The image can be used to align the light emitted by the endpoint detection system to a spot location within the alignment region, e.g., within an alignment opening of a substrate mounted on the substrate support member.

Abstract: A plasma processing system is described. The system may include a showerhead. The system may further include a first RF generator in electrical communication with the showerhead. The first RF generator may be configured to deliver a first voltage at a first frequency to the showerhead. Additionally, the system may include a second RF generator in electrical communication with a pedestal. The second RF generator may be configured to deliver a second voltage at a second frequency to the pedestal. The second frequency may be less than the first frequency. The system may also include a terminator in electrical communication with the showerhead. The terminator may provide a path to ground for the second voltage. Methods of depositing material using the plasma processing system are described. A method of seasoning a chamber by depositing silicon oxide and silicon nitride on the wall of the chamber is also described.

Abstract: Methods for pre-cleaning substrates having metal and dielectric surfaces are described. A substrate comprising a surface structure with a metal bottom, dielectric sidewalls, and a field of dielectric is exposed to a dual plasma treatment in a processing chamber to remove chemical residual and/or impurities from the metal bottom, the dielectric sidewalls, and/or the field of the dielectric and/or repair surface defects in the dielectric sidewalls and/or the field of the dielectric. The dual plasma treatment comprises a direct plasma and a remote plasma.

Abstract: Exemplary semiconductor processing chambers may include a gasbox. The chambers may include a substrate support. The chambers may include a blocker plate positioned between the gasbox and the substrate support. The blocker plate may define a plurality of apertures through the plate. The chambers may include a faceplate positioned between the blocker plate and substrate support. The faceplate may be characterized by a first surface facing the blocker plate and a second surface opposite the first surface. The second surface of the faceplate and the substrate support may at least partially define a processing region within the semiconductor processing chamber. The faceplate may be characterized by a central axis, and the faceplate may define a plurality of apertures through the faceplate. The faceplate may define a central recess about the central axis extending from the second surface of the faceplate to a depth less than a thickness of the faceplate.

Abstract: Described are methods for controlling the doping of metal nitride films such as TaN, TiN and MnN. The temperature during deposition of the metal nitride film may be controlled to provide a film density that permits a desired amount of doping. Dopants may include Ru, Cu, Co, Mn, Mo, Al, Mg, Cr, Nb, Ta, Ti and V. The metal nitride film may optionally be exposed to plasma treatment after doping.