Abstract: A method of polishing a layer on the substrate at a polishing station includes the actions of monitoring the layer during polishing at the polishing station with an in-situ monitoring system to generate a plurality of measured signals for a plurality of different locations on the layer; generating, for each location of the plurality of different locations, an estimated measure of thickness of the location, the generating including processing the plurality of measured signals through a neural network; and at least one of detecting a polishing endpoint or modifying a polishing parameter based on each estimated measure of thickness.

Abstract: Embodiment disclosed herein include a liner assembly, comprising an injector plate liner, a gas injector liner coupled to the injector plate liner, an upper process gas liner coupled to the gas injector liner, a lower process gas liner coupled to the upper process gas liner, and an injector plate positioned between the injector plate liner and the upper process gas liner, wherein a cooling fluid channel is formed in the injector plate adjacent to the gas injector liner.

Abstract: Methods are provided for manufacturing well-controlled, solid-state nanopores and arrays of well-controlled, solid-state nanopores by a cyclic process including atomic layer deposition (ALD), or chemical vapor deposition (CVD), and etching. One or more features are formed in a thin film deposited on a topside of a substrate. A dielectric material is deposited over the substrate having the one or more features in the thin film. An etching process is then used to etch a portion of the dielectric material deposited over the substrate having the one or more features in the thin film. The dielectric material deposition and etching processes are optionally repeated to reduce the size of the features until a well-controlled nanopore is formed through the thin film on the substrate.

Abstract: The present disclosure provides methods for performing an annealing process on a metal containing layer in TFT display applications, semiconductor or memory applications. In one example, a method of forming a metal containing layer on a substrate includes supplying an oxygen containing gas mixture on a substrate in a processing chamber, the substrate comprising a metal containing layer disposed on an optically transparent substrate, maintaining the oxygen containing gas mixture in the processing chamber at a process pressure between about 2 bar and about 50 bar, and thermally annealing the metal containing layer in the presence of the oxygen containing gas mixture.

Abstract: The use of a cyclic 1,4-diene reducing agent with a metal precursor and a reactant to form metal-containing films are described. Methods of forming the metal-containing film comprises exposing a substrate surface to a metal precursor, a reducing agent and a reactant either simultaneously, partially simultaneously or separately and sequentially to form the metal-containing film.

Abstract: Methods of depositing a film using a plasma enhanced process are described. The method comprises providing continuous power from a power source connected to a microwave plasma source in a process chamber and a dummy load, the continuous power split into pulses having a first time and a second time defining a duty cycle of a pulse. The continuous power is directed to the microwave plasma source during the first time, and the continuous power is directed to the dummy load during the second time.

Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a an absorber layer on the capping layer, the absorber layer made from an alloy of at least two absorber materials.

Abstract: Methods for the manufacture of extreme ultraviolet (EUV) mask blanks and production systems therefor are disclosed. A method for forming an EUV mask blank comprises forming a bilayer on a portion of a multi-cathode PVD chamber interior and then forming a multilayer stack of Si/Mo on a substrate in the multi-cathode PVD chamber.

Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture, and production systems therefor are disclosed. A method for forming an EUV mask blank comprises placing a substrate in a multi-cathode physical vapor deposition chamber, depositing a multilayer stack, removing the substrate from the chamber and passivating the PVD chamber.

Abstract: A carrier proximity mask and methods of assembling and using the carrier proximity mask may include providing a first carrier body, second carrier body, and set of one or more clamps. The first carrier body may have one or more openings formed as proximity masks to form structures on a first side of a substrate. The first and second carrier bodies may have one or more contact areas to align with one or more contact areas on a first and second sides of the substrate. The set of one or more clamps may clamp the substrate between the first carrier body and the second carrier body at contact areas to suspend work areas of the substrate between the first and second carrier bodies. The openings to define edges to convolve beams to form structures on the substrate.

Abstract: A monitoring circuit that includes a pickup loop to monitor a voltage applied to a cavity of a linear accelerator is disclosed. The monitoring circuit is electrically isolated from the linear accelerator and is also electrically isolated from the controller that receives input from the circuit and controls the linear accelerator. In certain embodiments, the monitoring circuit also includes an energy harvester so as to capture energy without any physical connection to the controller. This may be achieved using light energy or electromagnetic energy, for example. In certain embodiments, the monitoring circuit includes an analog-to-digital converter to convert the signals received from the pickup loop to digital values. In other embodiments, the monitoring circuit passes analog voltages to the controller. The outputs from the monitoring circuit may include the amplitude and phase of the voltage being applied to the respective cavity.

Abstract: A system for determining when a cleaning process has completed is disclosed. This system relies on an increase in the amount of gas in the processing chamber that occurs when the cleaning is complete. This increase in the amount of gas may be detected in several ways. In one embodiment, a downstream pendulum valve is used to maintain the pressure within the processing chamber at a predetermined value. An increase in the size of the opening in the pendulum valve is indicative of the amount of gas in the system. In another embodiment, a sensor may be used to monitor the pressure within the processing chamber, while the incoming and outgoing flow rates are held constant. An increase in the pressure is indicative of an increase in the amount of gas in the processing chamber. This increase in the amount of gas is used to terminate the cleaning process.

Abstract: Embodiments of the invention generally provide a cooling mechanism utilized in a plasma reactor that may provide efficient temperature control during a plasma process. In one embodiment, a cooling mechanism disposed in a plasma processing apparatus includes a coil antenna enclosure formed in a processing chamber, a coil antenna assembly disposed in the coil antenna enclosure, a plurality of air circulating elements disposed in the coil antenna enclosure adjacent to the coil antenna assembly, and a baffle plate disposed in the coil antenna enclosure below and adjacent to the coil antenna assembly.

Abstract: Electronic devices and methods of forming electronic devices with gate-all-around non-I/O devices and finlike structures for I/O devices are described. A plurality of dummy gates is etched to expose a fin comprising alternating layers of a first material and a second material. The second material layers are removed to create openings and the first material layers remaining are epitaxially grown to form a finlike structure.

Abstract: A method of detecting and classifying anomalies during semiconductor processing includes executing a wafer recipe a semiconductor processing system to process a semiconductor wafer; monitoring sensor outputs from a sensors that monitor conditions associated with the semiconductor processing system; providing the sensor outputs to models trained to identify when the conditions associated with the semiconductor processing system indicate a fault in the semiconductor wafer; receiving an indication of a fault from at least one of the models; and generating a fault output in response to receiving the indication of the fault.

Abstract: Semiconductor structures may include a substrate. The structures may include a gate structure overlying the substrate and formed in a first direction across the substrate. The structures may include a fin overlying the substrate and formed in a second direction across the substrate. The second direction may be orthogonal to the first direction, and the fin may intersect the gate structure. The structures may include a source/drain material formed about the fin. The structures may include a through-contact material extending vertically above the source/drain material. The structures may include a metal material extending vertically above the through-contact material. An interface between the metal material and the through-contact material may be characterized by a non-planar profile.

Abstract: Methods of etching film stacks to form gaps of uniform width are described. A film stack is etched through a hardmask. A conformal liner is deposited in the gap. The bottom of the liner is removed. The film stack is selectively etched relative to the liner. The liner is removed. The method may be repeated to a predetermined depth.

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a doped semiconductor material between source regions and drain regions of the device. The method includes doping semiconductor material layers between source regions and drain regions of an electronic device.

Abstract: A method may include providing a substrate in a plasma chamber, the substrate comprising a monocrystalline semiconductor, having an upper surface. The method may include initiating a plasma in the plasma chamber, the plasma comprising an amorphizing ion species, and applying a pulse routine to the substrate, the pulse routine comprising a plurality of extraction voltage pulses, wherein a plurality of ion pulses are directed to the substrate, and wherein an ion dose per pulse is greater than a threshold for low dose amorphization.

Abstract: A plasma processing apparatus is provided including a radio frequency power source; a direct current power source; a chamber enclosing a process volume; and a substrate support assembly disposed in the process volume. The substrate support assembly includes a substrate support having a substrate supporting surface; an electrode disposed in the substrate support; and an interconnect assembly coupling the radio frequency power source and the direct current power source with the electrode.