Abstract: Embodiments of magnetic tunnel junction (MTJ) structures discussed herein employ a first pinning layer and a second pinning layer with a synthetic anti-ferrimagnetic layer disposed therebetween. The first pinning layer in contact with the seed layer can contain a single layer of platinum or palladium, alone or in combination with one or more bilayers of cobalt and platinum (Pt), nickel (Ni), or palladium (Pd), or combinations or alloys thereof, The first pinning layer and the second pinning layer can have a different composition or configuration such that the first pinning layer has a higher magnetic material content than the second pinning layer and/or is thicker than the second pinning layer. The MTJ stacks discussed herein maintain desirable magnetic properties subsequent to high temperature annealing.

Abstract: Exemplary semiconductor processing systems may include a pedestal configured to support a semiconductor substrate. The pedestal may be operable as a first plasma-generating electrode. The systems may include a lid plate defining a radial volume. The systems may include a faceplate supported with the lid plate. The faceplate may be operable as a second plasma-generating electrode. A plasma processing region may be defined between the pedestal and the faceplate within the radial volume defined by the faceplate. The faceplate may define a plurality of first apertures. The systems may include a showerhead positioned between the faceplate and the pedestal. The showerhead may define a plurality of second apertures comprising a greater number of apertures than the plurality of first apertures.

Abstract: Exemplary deposition methods may include electrostatically chucking a semiconductor substrate at a first voltage within a processing region of a semiconductor processing chamber. The methods may include performing a deposition process. The deposition process may include forming a plasma within the processing region of the semiconductor processing chamber. The methods may include halting formation of the plasma within the semiconductor processing chamber. The methods may include, simultaneously with the halting, increasing the first voltage of electrostatic chucking to a second voltage. The methods may include purging the processing region of the semiconductor processing chamber.

Abstract: Embodiments of the present disclosure provide an improved electrostatic chuck for supporting a substrate. The electrostatic chuck comprises a chuck body coupled to a support stem, the chuck body having a substrate supporting surface, a plurality of tabs projecting from the substrate supporting surface of the chuck body, wherein the tabs are disposed around the circumference of the chuck body, an electrode embedded within the chuck body, the electrode extending radially from a center of the chuck body to a region beyond the plurality of tabs, and an RF power source coupled to the electrode through a first electrical connection.

Abstract: A load port includes a panel including a back surface configured to face a front side of a housing of a factory interface. A groove formed in the back surface extends along an outer portion of the panel. The groove includes a flared base region and a neck region that extends to the flared base region. The load port further includes a seal seated in the groove. The seal is configured to engage the front side of the housing responsive to the panel being coupled to the front side of the housing.

Abstract: Examples described herein generally relate to apparatus and methods for rapid thermal processing (RTP) of a substrate. In one or more embodiments, a process chamber includes chamber body, a window disposed on a first portion of the chamber body, a chamber bottom, and a shield disposed on a second portion of the chamber body. The shield has a flat surface facing the window to reduce reflected radiant energy to a back side of a substrate disposed in the process chamber during operation. The process chamber further includes an edge support for supporting the substrate and a cooling member disposed on the chamber bottom. The cooling member is disposed in proximity of the edge support to cool the edge support during low temperature operation in order to improve the temperature uniformity of the substrate.

Abstract: A method to assist in identifying a spectral feature and a characteristic of the selected spectral feature to monitor during polishing includes polishing a test substrate and measuring a sequence of spectra of light reflected from a substrate while the substrate is being polished, where at least some of the spectra of the sequence differ due to material being removed during the polishing. The sequence of spectra are visually displayed as a contour plot.

Abstract: A method and apparatus for delivering gases to a semiconductor processing system are provided. In some embodiments, the apparatus includes a gas inlet line having an inlet valve; a gas outlet line having an outlet valve; a gas flow controller arranged to control the flow through the inlet valve; an orifice contained within at least one of the gas outlet line, the outlet valve, a chemical ampoule outlet valve, or outlet isolation valve; a chemical ampoule fluidly coupled to at least one of the gas inlet line and the gas outlet line; and a processing chamber. In some embodiments, the apparatus further includes a check valve, one or more orifices, and/or a heated divert line.

Abstract: Embodiments described provide dynamic imaging systems that compensates for pattern defects resulting from distortion caused by warpage of the substrate. The methods and apparatus described are useful to create compensated exposure patterns. The dynamic imaging system includes an inspection system configured to provide 3D profile measurements and die shift measurements of the first substrate to the interface configured to provide compensated pattern data to the digital lithography system configured to receive the compensated pattern data from the interface and expose the photoresist with a compensated pattern.

Abstract: Embodiments of the present disclosure generally relate to methods and apparatus for depositing metal silicide layers on substrates and chamber components. In one embodiment, a method of forming a hardmask includes positioning the substrate having a target layer within a processing chamber, forming a seed layer comprising metal silicide on the target layer and depositing a tungsten-based bulk layer on the seed layer, wherein the metal silicide layer and the tungsten-based bulk layer form the hardmask. In another embodiment, a method of conditioning the components of a plasma processing chamber includes flowing an inert gas comprising argon or helium from a gas applicator into the plasma processing chamber, exposing a substrate support to a plasma within the plasma processing chamber and forming a seasoning layer including metal silicide on an aluminum-based surface of the substrate support.

Abstract: Embodiments of the disclosure provide an improved apparatus and methods for nitridation of stacks of materials. In one embodiment, a method for processing a substrate in a processing region of a process chamber is provided. The method includes generating and flowing plasma species from a remote plasma source to a delivery member having a longitudinal passageway, flowing plasma species from the longitudinal passageway to an inlet port formed in a sidewall of the process chamber, wherein the plasma species are flowed at an angle into the inlet port to promote collision of ions or reaction of ions with electrons or charged particles in the plasma species such that ions are substantially eliminated from the plasma species before entering the processing region of the process chamber, and selectively incorporating atomic radicals from the plasma species in silicon or polysilicon regions of the substrate.

Abstract: Embodiments of the present disclosure relate to methods for in-situ deposition and treatment of a thin film for improved step coverage. In one embodiment, the method for processing a substrate is provided. The method includes forming a dielectric layer on patterned features of the substrate by exposing the substrate to a gas mixture of a first precursor and a second precursor simultaneously with plasma present in a process chamber, wherein the plasma is formed by a first pulsed RF power, exposing the dielectric layer to a first plasma treatment using a gas mixture of nitrogen and helium in the process chamber, and performing a plasma etch process by exposing the dielectric layer to a plasma formed from a gas mixture of a fluorine-containing precursor and a carrier gas, wherein the plasma is formed in the process chamber by a second pulsed RF power.

Abstract: An apparatus, methods and controllers for electrostatically chucking varied substrate materials are disclosed. Some embodiments of the disclosure provide electrostatic chucks with variable polarity and/or voltage. Some embodiments of the disclosure provide electrostatic chucks able to operate as monopolar and bipolar electrostatic chucks. Some embodiments of the disclosure provide bipolar electrostatic chucks able to compensate for substrate bias and produce approximately equal chucking force at different electrodes.

Abstract: System and methods of improving dynamic pressure response during recipe step transitions. An exemplary method may include changing at least one of a plurality of recipe parameters in accordance with a processing recipe while running the processing recipe on a semiconductor substrate in a processing chamber. The method may further include measuring a pressure response in the processing chamber responsive to the changing of the at least one of the plurality of recipe parameters, and determining a response error based on the pressure response and a model pressure response calculated based on the processing recipe. The method may further include, in response to determining that the response error may be greater than a threshold value, calculating an adjustment to an operation of a valve downstream of the processing chamber when changing the at least one of the plurality of recipe parameters in accordance with the processing recipe in subsequent runs.

Abstract: Describes are shutter disks comprising one or more of titanium (Ti), barium (Ba), or cerium (Ce) for physical vapor deposition (PVD) that allows pasting to minimize outgassing and control defects during etching of a substrate. The shutter disks incorporate getter materials that are highly selective to reactive gas molecules, including O2, CO, CO2, and water.

Abstract: A system for measuring and controlling the phase of an incoming analog waveform is disclosed. The system comprises an analog to digital converter to convert the incoming analog waveform to a digital representation. The system also includes a clock delay generator, which allows a programmable amount of delay to be introduced into the sample clock for the ADC. The system further comprises a controller to manipulate the delay used by the clock delay generator and store the outputs from the ADC. The controller can then use the digitized representation to determine the frequency of the incoming analog waveform, its phase drift and its phase relative to a master clock. The controller can then modify the output of a RF generator in response to these determinations.

Abstract: Embodiments described herein include an applicator frame for a processing chamber. In an embodiment, the applicator frame comprises a first major surface of the applicator frame and a second major surface of the applicator frame opposite the first major surface. In an embodiment, the applicator frame further comprises a through hole, wherein the through hole extends entirely through the applicator frame. In an embodiment, the applicator frame also comprises a lateral channel embedded in the applicator frame. In an embodiment the lateral channel intersects the through hole.

Abstract: A semiconductor device is scanned by an electron beam of a scanning electron microscope (SEM). The area includes a three-dimensional (3D) feature having a top opening and a sidewall. The 3D feature is imaged while varying an energy value of the electron beam. The electron beam impinges at a first point within a selected area of the semiconductor device and interacts with the sidewall, wherein the first point is at a distance away from an edge of the top opening. Based on change in a signal representing secondary electron yield at the edge as the energy value of the electron beam is varied during the SEM imaging, it is determined whether the sidewall is occluded from a line-of-sight of the electron beam. A slope of the sidewall may be determined by comparing measured signals with simulated waveforms corresponding to various slopes.

Abstract: Implementations described herein provide a substrate support assembly that includes a seal band. The seal band protects an adhesive layer that is disposed between an electrostatic chuck (ESC) and a cooling plate of the substrate support assembly. In one example, a substrate support assembly includes an electrostatic chuck and a cooling plate. A bonding layer secures a bottom surface of the electrostatic chuck to a top surface of the cooling plate. The bonding layer has an adhesive layer and a seal band. The seal band circumscribes and protects the adhesive layer. The seal band has a ring shaped body. The ring shaped body has a top surface connected to a bottom surface by an inner surface and an outer surface. The top surface and the bottom surface angled less than 85 degrees from the inner surface. The outer surface has an indent formed therein.

Abstract: Embodiments include methods and systems of 3D structure fill. In one embodiment, a method of filling a trench in a wafer includes performing directional plasma treatment with an ion beam at an angle with respect to a sidewall of the trench to form a treated portion of the sidewall and an untreated bottom of the trench. A material is deposited in the trench. The deposition rate of the material on the treated portion of the sidewall is different than a second deposition rate on the untreated bottom of the trench. In one embodiment, a method includes depositing a material on the wafer, filling a bottom of the trench and forming a layer on a sidewall of the trench and a top surface adjacent to the trench. The method includes etching the layer with an ion beam at an angle with respect to the sidewall.