Abstract: Exemplary methods of forming semiconductor structures may include forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor. The methods may include forming a silicon nitride layer from a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor. The silicon nitride layer may be characterized by an oxygen concentration greater than or about 5 at. %. The methods may also include repeating the forming a silicon oxide layer and the forming a silicon nitride layer to produce a stack of alternating layers of silicon oxide and silicon nitride.

Abstract: Techniques for deposition of high-density dielectric films for patterning applications are described. More particularly, a method of processing a substrate is provided. The method includes flowing a precursor-containing gas mixture into a processing volume of a processing chamber having a substrate positioned on an electrostatic chuck. The substrate is maintained at a pressure between about 0.1 mTorr and about 10 Torr. A plasma is generated at the substrate level by applying a first RF bias to the electrostatic chuck to deposit a dielectric film on the substrate. The dielectric film has a refractive index in a range of about 1.5 to about 3.

Abstract: Processing platforms having a central transfer station with a robot and an environment having greater than or equal to about 0.1% by weight water vapor, a pre-clean chamber connected to a side of the transfer station and a batch processing chamber connected to a side of the transfer station. The processing platform configured to pre-clean a substrate to remove native oxides from a first surface, form a blocking layer using a alkylsilane and selectively deposit a film. Methods of using the processing platforms and processing a plurality of wafers are also described.

Abstract: Embodiments of the present disclosure relate to forming a two-dimensional crystalline dichalcogenide by positioning a substrate in an annealing apparatus. The substrate includes an amorphous film of a transition metal and a chalcogenide. The film is annealed at a temperature from 500° C. to 1200° C. In response to the annealing, a two-dimensional crystalline structure is formed from the film. The two-dimensional crystalline structure is according to a formula MX2, M includes one or more of molybdenum (Mo) or tungsten (W) and X includes one or more of sulfur (S), selenium (Se), or tellurium (Te).

Abstract: An electronic device manufacturing system includes a motion control system for calibrating a gap between surfaces of process chamber or loadlock components by moving those component surfaces into direct contact with each other. The component surfaces may include a surface of a substrate and/or a substrate support and a surface of process delivery apparatus, which may be, e.g., a pattern mask and/or a plasma or gas distribution assembly. The motion control system may include a motion controller, a software program executable by the motion controller, a network, one or more actuator drivers, a software program executable by the one or more actuator drivers, one or more actuators, and one or more feedback devices. Methods of calibrating a gap via direct contact of process chamber or loadlock component surfaces are also provided, as are other aspects.

Abstract: Implementations described herein generally relate to low melting temperature metal or alloy metal deposition and processing. More particularly, the implementations described herein relate to methods and systems for low melting temperature metal or alloy metal deposition and processing for printed electronics and electrochemical devices. In yet another implementation, a method is provided. The method comprises exposing a molten metal source to a purification process to remove unwanted quantities of contaminants, delivering the filtered molten metal to a three dimensional printing device, and forming a metal film on a substrate by printing the filtered molten metal on the substrate. The purification process comprises delivering the molten metal to a filter assembly, wherein the filter assembly includes at least one of: a skimmer device, a metal mesh filter, and a foam filter, and filtering the molten metal through the filter assembly.

Abstract: Embodiments of this disclosure describe a feedback loop that can be used to maintain a nearly constant sheath voltage and thus creating a mono-energetic IEDF at the surface of the substrate. The system described herein consequently enables a precise control over the shape of IEDF and the profile of the features formed in the surface of the substrate.

Abstract: Embodiments of the present disclosure generally relate to methods for conditioning an interior wall surface of a remote plasma generator. In one embodiment, a method for processing a substrate is provided. The method includes exposing an interior wall surface of a remote plasma source to a conditioning gas that is in excited state to passivate the interior wall surface of the remote plasma source, wherein the remote plasma source is coupled through a conduit to a processing chamber in which a substrate is disposed, and the conditioning gas comprises an oxygen-containing gas, a nitrogen-containing gas, or a combination thereof. The method has been observed to be able to improve dissociation/recombination rate and plasma coupling efficiency in the processing chamber, and therefore provides repeatable and stable plasma source performance from wafer to wafer.

Abstract: A processing chamber may include a gas distribution member, a metal ring member below the gas distribution member, and an isolating assembly coupled with the metal ring member and isolating the metal ring member from the gas distribution member. The isolating assembly may include an outer isolating member coupled with the metal ring member. The outer isolating member may at least in part define a chamber wall. The isolating assembly may further include an inner isolating member coupled with the outer isolating member. The inner isolating member may be disposed radially inward from the metal ring member about an central axis of the processing chamber. The inner isolating member may define a plurality of openings configured to provide fluid access into a radial gap between the metal ring member and the inner isolating member.

Abstract: Exemplary support assemblies may include an electrostatic chuck body defining a substrate support surface. The assemblies may include a support stem coupled with the electrostatic chuck body. The assemblies may include a heater embedded within the electrostatic chuck body. The assemblies may also include an electrode embedded within the electrostatic chuck body between the heater and the substrate support surface. The substrate support assemblies may be characterized by a leakage current through the electrostatic chuck body of less than or about 4 mA at a temperature of greater than or about 500° C. and a voltage of greater than or about 600 V.

Abstract: A semiconductor device that implements artificial neurons and synapses together on the semiconductor device includes a plurality of fins formed on the semiconductor device, and a plurality of gates formed around the plurality of fins to form a plurality of fin field-effect transistors (FinFETs). The plurality of FinFETs may form one or more artificial synapses and one or more artificial neurons. Each of the one or more artificial synapses may include two or more of the plurality of gates. Each of the one or more artificial neurons comprises one of the plurality of gates.

Abstract: Described are isolation valves, and chamber systems incorporating and methods of using the isolation valves. In some embodiments, an isolation valve may include a valve body and a flapper assembly. The valve body may define a first fluid volume, a second fluid volume, and a seating surface. The flapper assembly may include a flapper disposed inside the valve body having a flapper surface complimentary to the seating surface. The flapper may be pivotable within the valve body to a first position such that the flapper surface may be away from the seating surface to allow fluid flow between the first fluid volume and the second fluid volume. The flapper may be pivotable within the valve body to a second position such that the flapper surface may be proximate the seating surface to form a non-contact seal to restrict fluid flow between the first fluid volume and the second fluid volume.

Abstract: Described are semiconductor devices, methods of manufacturing, and methods for device patterning. More particularly, a subtractive interconnect patterning method is described. A subtractive interconnect patterning is used in place of damascene interconnect patterning.

Abstract: A processing chamber may include a gas distribution member, a substrate support, and a pumping liner. The gas distribution member and the substrate support may at least in part define a processing volume. The pumping liner may define an internal volume in fluid communication with the processing volume via a plurality of apertures of the pumping liner circumferentially disposed about the processing volume. The processing chamber may further include a flow control mechanism operable to direct fluid flow from the internal volume of the pumping liner into the processing volume via a subset of the plurality of apertures of the pumping liner during fluid distribution into the processing volume from the gas distribution member.

Abstract: Methods of depositing an encapsulation stack without damaging underlying layers are discussed. The encapsulation stacks are highly conformal, have low etch rates, low atomic oxygen concentrations, good hermeticity and good adhesion. These films may be used to protect chalcogen materials in PCRAM devices. Some embodiments utilize a two-step process comprising a first ALD process to form a protective layer and a second plasma ALD process to form an encapsulation layer.

Abstract: Methods of cleaning a PVD chamber component, for example, process kit components are disclosed. The method comprises at least one of directing a jet of pressurized fluid at a surface of the PVD chamber component, directing pressurized carbon dioxide at the surface of the PVD chamber component, placing the PVD chamber component in a liquid and producing ultrasonic waves in the liquid to further remove contaminants from the surface of the PVD chamber component, using a plasma to clean the surface of the PVD chamber component, subjecting the PVD chamber component to a thermal cycle by heating up to a peak temperature of at least 50° C.

Abstract: Methods of forming a DRAM bit line to improve line edge roughness (LER) and lower resistance are described. The method comprises implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed.

Abstract: Apparatuses and methods to provide a patterned substrate are described. A plurality of patterned and spaced first lines and carbon material lines and formed on the substrate surface by selectively depositing and etching films extending in a first direction and films extending in a second direction that crosses the first direction to pattern the underlying structures.

Abstract: A cleanliness monitor for monitoring a cleanliness of a vacuum chamber. The cleanliness monitor may include a mass spectrometer, a molecule aggregation and release unit and an analyzer. The molecule aggregation and release unit is configured to (a) aggregate, during an aggregation period, organic molecules that are present in the vacuum chamber and (b) induce, during a release period, a release of a subset of the organic molecules towards the mass spectrometer. The mass spectrometer is configured to monitor an environment within the vacuum chamber and to generate detection signals indicative of a content of the environment; wherein a first subset of the detection signals is indicative of a presence of the subset of the organic molecules. The analyzer is configured to determine the cleanliness of the vacuum chamber based on the detection signals.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.