Abstract: The present invention relates to a method for manufacturing an electrostatic chuck comprising: a base member of a metal material; and a dielectric layer, formed on an upper surface of the base member, including an electrode layer to the inside of which a DC power is applied. According to the present invention, the dielectric layer is formed of a ceramic material by using at least one selected from among a plasma spraying method and a sol-gel method, and thus can be provided with low porosity to increase in lifespan, and with high permittivity to increase in adhesion force to a substrate.

Abstract: A method and apparatus to determine a temperature of a substrate using a spectrum of radiation is disclosed herein. In one aspect, a process chamber includes a lamp assembly optically coupled to a spectrometer. The spectrometer is used to determine a temperature of a substrate within the process chamber. A controller is coupled to the spectrometer and controls the lamp assembly to selectively heat and cool the substrate. In another aspect, a method of includes exposing a substrate to a radiation source. A spectrum of radiation is detected by a spectrometer across a substrate. The spectrum of radiation passed through the substrate is determined and used to determine a temperature of the substrate.

Abstract: Processing methods comprising selectively replacing a first pillar material with a second pillar material in a self-aligned process are described. The first pillar material may be grown orthogonally to the substrate surface and replaced with a second pillar material to leave a substantially similar shape and alignment as the first pillar material.

Abstract: Embodiments of the present disclosure provide a sputtering chamber with in-situ ion implantation capability. In one embodiment, the sputtering chamber comprises a target, an RF and a DC power supplies coupled to the target, a support body comprising a flat substrate receiving surface, a bias power source coupled to the support body, a pulse controller coupled to the bias power source, wherein the pulse controller applies a pulse control signal to the bias power source such that the bias power is delivered either in a regular pulsed mode having a pulse duration of about 100-200 microseconds and a pulse repetition frequency of about 1-200 Hz, or a high frequency pulsed mode having a pulse duration of about 100-300 microseconds and a pulse repetition frequency of about 200 Hz to about 20 KHz, and an exhaust assembly having a concentric pumping port formed through a bottom of the processing chamber.

Abstract: A method of forming a three-dimensional transistor device. The method may include providing a fin array on a substrate, the fin array comprising a plurality of fin structures, formed from a monocrystalline semiconductor, and disposed subjacent to a hard mask layer. The method may include directing angled ions at the fin array, wherein the angled ions form a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate. The angled ions may etch the plurality of fin structures to form a stack of isolated nanowires, within a given fin structure.

Abstract: Embodiments include an electrostatic chuck assembly having an electrostatic chuck mounted on an insulator. The electrostatic chuck and insulator may be within a chamber volume of a process chamber. In an embodiment, a ground shield surrounds the electrostatic chuck and the insulator, and a gap between the ground shield and the electrostatic chuck provides an environment at risk for electric field emission. A dielectric filler can be placed within the gap to reduce a likelihood of electric field emission. The dielectric filler can have a flexible outer surface that covers or attaches to the electrostatic chuck, or an interface between the electrostatic chuck and the insulator Other embodiments are also described and claimed.

Abstract: Disclosed are methods of forming devices. One method may include providing a first set of fins and a second set of fins extending from a substrate, and providing a dummy oxide over the first set of fins and the second set of fins. The method may further include performing a thermal implant to the second set of fins, wherein the thermal implant is an angled ion implant impacting the dummy oxide. The method may further include removing the dummy oxide from the first set of fins and the second set of fins, and forming a first work function (WF) metal over the first set of fins and a second WF metal over the second set of fins.

Abstract: Methods of forming and processing semiconductor devices which utilize a three-color process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts utilizing selective deposition of overlapping masks in a three-color process.

Abstract: Embodiments of the present disclosure generally provide apparatus and methods for removing an attachment feature utilized to hold a pellicle from a photomask. In one embodiment, an attachment feature removal apparatus for processing a photomask includes an attachment feature puller comprising an actuator, a clamp coupled to the actuator, the clamp adapted to grip an attachment feature, and a coil assembly disposed adjacent to the attachment feature.

Abstract: Methods and systems for controlling temperatures in plasma processing chamber via pulsed application of heating power and pulsed application of cooling power. In an embodiment, fluid levels in each of a hot and cold reservoir coupled to the temperature controlled component are maintained in part by a coupling each of the reservoirs to a common secondary reservoir. Heat transfer fluid is pumped from the secondary reservoir to either the hot or cold reservoir in response to a low level sensed in the reservoir. In an embodiment, both the hot and cold reservoirs are contained in a same platform as the secondary reservoir with the hot and cold reservoirs disposed above the secondary reservoir to permit the secondary reservoir to catch gravity driven overflow from either the hot or cold reservoir.

Abstract: Methods and apparatus for forming a metal silicide as nanowires for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes forming a metal silicide layer on a substrate by a chemical vapor deposition process or a physical vapor deposition process, thermal treating the metal silicide layer in a processing chamber, applying a microwave power in the processing chamber while thermal treating the metal silicide layer; and maintaining a substrate temperature less than 400 degrees Celsius while thermal treating the metal silicide layer. In another embodiment, a method includes supplying a deposition gas mixture including at least a metal containing precursor and a reacting gas on a surface of a substrate, forming a plasma in the presence of the deposition gas mixture by exposure to microwave power, exposing the plasma to light radiation, and forming a metal silicide layer on the substrate from the deposition gas.

Abstract: Embodiments described herein generally relate to methods of depositing thin films and, more particularly, to depositing metal thin films. The methods herein provide a nucleation free conversion (NFC) approach which involves forming an amorphous silicon layer over the dielectric layer, and performing an NFC process which acts to convert the amorphous silicon layer into a thin metal film. In some embodiments, the NFC process is performed multiple times until the resulting thin metal film is continuous. A bulk metal is formed over the thin metal film.

Abstract: In one embodiment, a susceptor for thermal processing is provided. The susceptor includes an outer rim surrounding and coupled to an inner dish, the outer rim having an inner edge and an outer edge. The susceptor further includes one or more structures for reducing a contacting surface area between a substrate and the susceptor when the substrate is supported by the susceptor. At least one of the one or more structures is coupled to the inner dish proximate the inner edge of the outer rim.

Abstract: Systems and methods for controlling device performance variability during manufacturing of a device on wafers are disclosed. The system includes a process platform, on-board metrology (OBM) tools, and a first server that stores a machine-learning based process control model. The first server combines virtual metrology (VM) data and OBM data to predict a spatial distribution of one or more dimensions of interest on a wafer. The system further comprises an in-line metrology tool, such as SEM, to measure the one or more dimensions of interest on a subset of wafers sampled from each lot. A second server having a machine-learning engine receives from the first server the predicted spatial distribution of the one or more dimensions of interest based on VM and OBM, and also receives SEM metrology data, and updates the process control model periodically (e.g., wafer-to-wafer, lot-to-lot, chamber-to-chamber etc.) using machine learning techniques.

Abstract: Data indicative of location information of a potential defect of interest revealed in a specimen and of one or more layers of the specimen corresponding to the potential defect of interest may be received. A die layout clip may be generated in accordance with the data by deriving the die layout clip based on the location information of the potential defect of interest and the one or more layers of the specimen corresponding to the potential defect of interest. The die layout clip may include information indicative of one or more patterns characterizing an inspection area that includes the potential defect of interest of the specimen. The generated die layout clip may be transmitted to a semiconductor inspection unit where an inspection by the semiconductor inspection unit of a semiconductor wafer that includes the specimen corresponding to the potential defect of interest is based on the one or more patterns of the die layout clip.

Abstract: Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts utilizing selective deposition of masks in a three-color process.

Abstract: Exemplary semiconductor processing chambers may include a showerhead. The chambers may also include a substrate support characterized by a first surface facing the showerhead. The first surface may be configured to support a semiconductor substrate. The substrate support may define a recessed pocket centrally located within the first surface. The recessed pocket may be defined by an outer radial wall characterized by a height from the first surface within the recessed pocket that is greater than or about 150% of a thickness of the semiconductor substrate.

Abstract: A method of depositing titanium nitride is disclosed. Some embodiments of the disclosure provide a PEALD process for depositing titanium nitride which utilizes a direct microwave plasma. In some embodiments, the direct microwave plasma has a high plasma density and low ion energy. In some embodiments, the plasma is generated directly above the substrate surface.

Abstract: Methods for deposition of high-hardness low-? dielectric films are described. More particularly, a method of processing a substrate is provided. The method includes flowing a precursor-containing gas mixture into a processing volume of a processing chamber having a substrate, the precursor having the general formula (I) wherein R1, R2, R3, R4, R5, R6, R7, and R8 are independently selected from hydrogen (H), alkyl, alkoxy, vinyl, silane, amine, or halide; maintaining the substrate at a pressure in a range of about 0.1 mTorr and about 10 Torr and at a temperature in a range of about 200° C. to about 500° C.; and generating a plasma at a substrate level to deposit a dielectric film on the substrate.

Abstract: A method of forming a molybdenum film by oxidation and reduction is disclosed. A molybdenum oxide film is formed by CVD or ALD using a halide free organometallic molybdenum precursor. The molybdenum oxide film contains low amounts of carbon impurities. The molybdenum oxide film is reduced to form a highly pure molybdenum film. The molybdenum film has low resistance and properties similar to bulk molybdenum.