Patents Assigned to Applied Material
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Patent number: 12183548Abstract: Embodiments disclosed herein include a processing tool. In an embodiment, the processing tool comprises a power supply, an impedance matching network coupled to the power supply, a cathode, wherein the power supply is configured to supply power through the impedance matching network to the cathode, and a processing module, wherein the processing module is communicatively coupled to the power supply and the impedance matching network.Type: GrantFiled: May 5, 2022Date of Patent: December 31, 2024Assignee: Applied Materials, Inc.Inventor: David Coumou
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Patent number: 12181736Abstract: Embodiments of metasurfaces having nanostructures with desired geometric profiles and configurations are provided in the present disclosure. In one embodiment, a metasurface includes a nanostructure formed on a substrate, wherein the nanostructure is cuboidal or cylindrical in shape. In another embodiment, a metasurface includes a plurality of nanostructures on a substrate, wherein each of the nanostructures has a gap greater than 35 nm spaced apart from each other. In yet another embodiment, a metasurface includes a plurality of nanostructures on a substrate, wherein the nanostructures are fabricated from at least one of TiO2, silicon nitride, or amorphous silicon, or GaN or aluminum zinc oxide or any material with refractive index greater than 1.8, and absorption coefficient smaller than 0.001, the substrate is transparent with absorption coefficient smaller than 0.001.Type: GrantFiled: October 31, 2022Date of Patent: December 31, 2024Assignee: Applied Materials, Inc.Inventors: Tapashree Roy, Wayne McMillan, Rutger Meyer Timmerman Thijssen
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Patent number: 12185433Abstract: A substrate support assembly includes a plate structure and an insulator structure. The plate structure includes an upper plate and a lower plate. The lower plate includes a lower plate structure surface. The insulator structure is disposed beneath the plate structure. The insulator structure includes a lower insulator structure surface and an upper insulator structure surface. A first portion of the upper insulator structure surface is recessed with respect to a second portion of the upper insulator structure surface. The first portion of the upper insulator structure surface forms an interior volume with the lower plate structure surface.Type: GrantFiled: May 15, 2023Date of Patent: December 31, 2024Assignee: Applied Materials, Inc.Inventors: Denis Martin Koosau, Suresh Gupta, Martin Perez-Guzman, Ashish Goel
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Patent number: 12183794Abstract: Methods may include providing a device structure having a shielding layer formed beneath each trench in a MOSFET to protect trench corner breakdown. The method may include providing a device structure comprising an epitaxial layer, a well over the epitaxial layer, and a source layer over the well, and providing a plurality of trenches through the device structure. The method may further include forming a shielding layer in the device structure by directing ions into the plurality of trenches.Type: GrantFiled: August 6, 2021Date of Patent: December 31, 2024Assignee: Applied Materials, Inc.Inventors: Qintao Zhang, Samphy Hong
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Patent number: 12183684Abstract: The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor device package. In certain embodiments, a glass or silicon substrate is patterned by laser ablation to form structures for subsequent formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor device package, which may have one or more embedded dies therein. In certain embodiments, an insulating layer is formed over the substrate by laminating a pre-structured insulating film thereon. The insulating film may be pre-structured by laser ablation to form structures therein, followed by selective curing of sidewalls of the formed structures.Type: GrantFiled: October 26, 2021Date of Patent: December 31, 2024Assignee: Applied Materials, Inc.Inventors: Mukhles Sowwan, Samer Banna
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Patent number: 12183553Abstract: The present disclosure generally relates to an apparatus for improving azimuthal uniformity of a pressure profile of a processing gas. In one example, a processing chamber includes a lid, sidewalls, and a substrate support defining a processing volume. A bottom bowl, a chamber base, and a wall define a purge volume. The purge volume is disposed beneath the processing volume. The bottom bowl includes a first surface having a first equalizer hole. A passage couples the processing volume to the purge volume via the first equalizer hole and an inlet. The passage is positioned above the first equalizer hole. The chamber base has a purge port coupleable to a purge gas line for supplying a purge gas to the purge volume. A baffle is disposed in the purge volume at a height above the purge port, and is configured to deflect a trajectory of the purge gas.Type: GrantFiled: June 3, 2020Date of Patent: December 31, 2024Assignee: Applied Materials, Inc.Inventors: Nitin Pathak, Kartik Shah, Amit Kumar Bansal, Tuan Anh Nguyen, Juan Carlos Rocha, David Blahnik
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Publication number: 20240424685Abstract: A substrate safety system that includes (i) a control unit that is configured to trigger a substrate recovery related procedure; (ii) a sensing unit that is configured to generate, during an execution of the substrate recovery related procedure, sensed information that is indicative of one or more regions that are associated with a substrate handling station of a substrate evaluation system; (iii) an AI processing unit that is configured to apply an AI process on the sensed information to determine a recovery related status of the substrate; and (iv) a response unit that is configured to respond to the recovery related status of the substrate.Type: ApplicationFiled: June 26, 2023Publication date: December 26, 2024Applicant: Applied Materials lsrael Ltd.Inventors: Binyamin Bejell, Itamar Orenbuch, Avi Aboodi
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Publication number: 20240429048Abstract: A semiconductor device and a method for manufacturing thereof. A substrate is provided. At least one silicon layer is formed on top of the substrate. At least one silicon-germanium layer is formed on top of at least one silicon layer. At least one silicon-germanium layer includes at least one n-type dopant. The semiconductor device having at least one silicon layer and at least one silicon-germanium layer is formed.Type: ApplicationFiled: June 17, 2024Publication date: December 26, 2024Applicant: Applied Materials, Inc.Inventors: Ruiying HAO, Thomas KIRSCHENHEITER, Arvind KUMAR, Mahendra PAKALA, Roya BAGHI, Balasubramanian PRANATHARTHIHARAN, Fredrick FISHBURN
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Publication number: 20240425536Abstract: Exemplary methods of semiconductor processing, such as methods of depositing a molybdenum-containing material on a substrate, may include providing a molybdenum-containing precursor to a processing region of a semiconductor processing chamber in which the substrate is located. The molybdenum-containing precursor may include a molybdenum complex according to Compound I: R may be methyl or ethyl, R? may be methyl or ethyl, R? may be methyl, ethyl, or propyl, and n may be equal to 1 or 2. Contacting the substrate with the molybdenum-containing precursor may deposit the molybdenum-containing material on the substrate.Type: ApplicationFiled: June 13, 2023Publication date: December 26, 2024Applicant: Applied Materials, Inc.Inventors: Feng Q. Liu, Mark J. Saly, David Thompson
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Publication number: 20240429062Abstract: Exemplary methods of semiconductor processing may include providing a hydrogen-containing precursor and a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed on a substrate support within the processing region. One or more layers of silicon-containing material may be disposed on the substrate. The methods may include forming plasma effluents of the hydrogen-containing precursor and the fluorine-containing precursor. The methods may include contacting one or more layers of silicon-containing material with plasma effluents of the hydrogen-containing precursor and the fluorine-containing precursor. The contacting may etch a portion of the one or more layers of silicon-containing material.Type: ApplicationFiled: June 21, 2023Publication date: December 26, 2024Applicant: Applied Materials, Inc.Inventors: Alok Ranjan, Anatoli Chlenov, Kenji Takeshita
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Publication number: 20240431093Abstract: The present technology is generally directed to vertical dynamic random-access memory (DRAM) cells and arrays, and methods of forming such cells and arrays, that contain a shared word line between two adjacent channels. Cells include a bit line arranged in a first horizontal direction, a first channel, a second channel, and a shared word line arranged in a second horizontal direction between the first channel and the second channel. Cells include where the first channel and the second channel extend in a vertical direction that is orthogonal to the first horizontal direction and the second horizontal direction, such that the bit line intersects with a source/drain region of the first channel and the second channel, and the shared word line intersects with a gate region of both the first channel and the second channel.Type: ApplicationFiled: June 4, 2024Publication date: December 26, 2024Applicant: Applied Materials, Inc.Inventor: Fredrick Fishburn
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Publication number: 20240429105Abstract: Disclosed herein are approaches for measuring lateral dopant concentration and distribution in high aspect radio trench structures. In one approach, a method may include providing a substrate including a plurality of alternating vertical structures and trenches, and removing a portion of the substrate to expose a sidewall of the first vertical structure of the plurality of structures. The method may further include directing a spectrometry beam into the sidewall of the first vertical structure to determine a dopant characteristic of the first vertical structure, wherein the spectrometry beam is delivered perpendicular to a plane defined by the sidewall of the first vertical structure.Type: ApplicationFiled: June 20, 2023Publication date: December 26, 2024Applicant: Applied Materials, Inc.Inventors: Dimitry KOUZMINOV, Vikram M. BHOSLE, Arun Ramaswamy SRIVATSA, Ming Hong YANG
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Patent number: 12173413Abstract: Methods of processing thin film by oxidation at high pressure are described. The methods are generally performed at pressures greater than 2 bar. The methods can be performed at lower temperatures and have shorter exposure times than similar methods performed at lower pressures. Some methods relate to oxidizing tungsten films to form self-aligned pillars.Type: GrantFiled: September 13, 2021Date of Patent: December 24, 2024Assignee: Applied Materials, Inc.Inventors: Amrita B. Mullick, Pramit Manna, Abhijit Basu Mallick
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Patent number: 12175656Abstract: A method for gray level ratio inspection comprising: obtaining an electron image that comprises region of interest (ROI) pixels of a ROI of the sample and reference pixels of a reference region of the sample, where the ROI pixels are obtained by illuminating the ROI with the electron beam and the reference pixels are obtained without illuminating the reference region with an electron beam; calculating a reference dark level value based on values of at least some of the reference pixels; calculating, responsive to the reference dark level value, a gray level ratio between a first gray level value related to a first sub-set of the ROI pixels and a second gray level value related to a second sub-set of the ROI pixels; determining whether the gray level ratio is indicative of a defect; and generating defect information following a determination that the gray level ratio is indicative of the defect.Type: GrantFiled: February 23, 2022Date of Patent: December 24, 2024Assignee: Applied Materials Israel Ltd.Inventors: Effi Siman tov, Udi Abrahamov
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Patent number: 12176188Abstract: Embodiments disclosed herein include a diagnostic substrate. In an embodiment, the diagnostic substrate comprises a substrate, a circuit board on the substrate, and a spectrometer coupled to the circuit board. In an embodiment, the diagnostic substrate further comprises a processor on the circuit board and communicatively coupled to the spectrometer.Type: GrantFiled: April 7, 2022Date of Patent: December 24, 2024Assignee: Applied Materials, Inc.Inventors: Chuang-Chia Lin, Wenwei Qiao
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Patent number: 12176205Abstract: Embodiments of the present disclosure generally relate to methods and apparatus for backside stress engineering of substrates to combat film stresses and bowing issues. In one embodiment, a method of depositing a film layer on a backside of a substrate is provided. The method includes flipping a substrate at a factory interface so that the backside of the substrate is facing up, and transferring the flipped substrate from the factory interface to a physical vapor deposition chamber to deposit a film layer on the backside of the substrate. In another embodiment, an apparatus for depositing a backside film layer on a backside of a substrate, which includes a substrate supporting surface configured to support the substrate at or near the periphery of the substrate supporting surface without contacting an active region on a front side of the substrate.Type: GrantFiled: June 19, 2023Date of Patent: December 24, 2024Assignee: Applied Materials, Inc.Inventors: Chunming Zhou, Jothilingam Ramalingam, Yong Cao, Kevin Vincent Moraes, Shane Lavan
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Patent number: 12178146Abstract: Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.Type: GrantFiled: March 28, 2023Date of Patent: December 24, 2024Assignee: Applied Materials, Inc.Inventors: Deepak Kamalanathan, Archana Kumar, Siddarth Krishnan
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Patent number: 12176384Abstract: A method of transferring micro-devices includes selectively treating a first adhesive layer to form a treated portion and an untreated portion while micro-devices are attached the first adhesive layer. A second adhesive layer on a second surface is placed to abut the micro-devices. The first adhesive layer is exposed to illumination in a region that overlaps at least some of the treated portion and at least some of the untreated portion. Exposing the first adhesive layer to illumination neutralizes the at least some of the untreated portion to create a neutralized portion that is less adhesive than an exposed area of the treated portion. The first surface is separated from the second surface such that micro-devices in the treated portion remain attached to the first surface and micro-devices in the neutralized portion are attached to the second surface and separate from the first surface.Type: GrantFiled: August 16, 2023Date of Patent: December 24, 2024Assignee: Applied Materials, Inc.Inventors: Manivannan Thothadri, Arvinder Chadha
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Patent number: 12173807Abstract: A system includes a mounting panel having diffusion-bonded metal plates that form a reservoir to contain a process fluid, multiple channels through which to flow the process fluid, and vias through which to flow the process fluid to and from process fluid control components attached to the mounting panel. At least a pair of the multiple channels are connected with the reservoir. A temperature sensor is attached to a top of the mounting panel, the temperature sensor in fluid communication with the reservoir through one of the vias. A set of inlet ports are attached to the mounting panel, the set of inlet ports to receive the process fluid. At least one outlet port is attached to the mounting panel, the at least one outlet port to output the process fluid from the mounting panel.Type: GrantFiled: March 21, 2023Date of Patent: December 24, 2024Assignee: Applied Materials, Inc.Inventors: Sohrab Zokaei, Kiran Garikipati, Shawn Thanhsan Le
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Patent number: D1055006Type: GrantFiled: March 18, 2022Date of Patent: December 24, 2024Assignee: Applied Materials, Inc.Inventors: Sahiti Nallagonda, Jonathan Simmons, Xinwei Huang, Peter Muraoka, Andreas Schmid
