Abstract: Methods are disclosed for fabricating a compound nitride semiconductor structure. An amorphous buffer layer that includes nitrogen and a group-III element is formed over a substrate disposed within a substrate processing chamber at a first temperature. The temperature within the chamber is increased to a second temperature at which the amorphous buffer layer coalesces into crystallites over the substrate. The substrate is exposed to a corrosive agent to destroy at least some of the crystallites. A crystalline nitride layer is formed over the substrate at a third temperature using the crystallites remaining after exposure to the corrosive agent as seed crystals. The third temperature is greater than the first temperature. The crystalline nitride layer also includes nitrogen and a group-III element.

Abstract: Embodiments of the invention generally provide a method for depositing a film containing silicon (Si) and nitrogen (N). In one embodiment, the method includes heating a substrate disposed in a processing chamber to a temperature less than about 650 degrees Celsius, flowing a nitrogen-containing gas into the processing chamber, flowing a silicon-containing gas into the processing chamber, and depositing a SiN-containing layer on a substrate. The silicon-containing gas is at least one of a gas identified as NR2—Si(R?2)—Si(R?2)—NR2 (amino(di)silanes), R3—Si—N?N?N (silyl azides), R?3—Si—NR—NR2 (silyl hydrazines) or 1,3,4,5,7,8-hexamethytetrasiliazane, wherein R and R? comprise at least one functional group selected from the group of a halogen, an organic group having one or more double bonds, an organic group having one or more triple bonds, an aliphatic alkyl group, a cyclical alkyl group, an aromatic group, an organosilicon group, an alkyamino group, or a cyclic group containing N or Si.

Abstract: A dilution stage is adapted to supply a dilute chemistry to a semiconductor device processing apparatus. The dilution stage includes a first vessel adapted to store the chemistry after dilution and a second vessel adapted to store the chemistry prior to dilution. The dilution stage may also include a control mechanism which is adapted to selectively control flowing of the chemistry and a dilutant to the first vessel. The control mechanism may be operative to fill the second vessel with the chemistry, and to flow the dilutant to the first vessel via the second vessel.

Abstract: We have reduced the critical dimension bias for reticle fabrication. Pattern transfer to the radiation-blocking layer of the reticle substrate essentially depends upon use of a hard mask to which the pattern is transferred from a photoresist. The photoresist pull back which occurs during pattern transfer to the hard mask is minimalized. In addition, a hard mask material having anti-reflective properties which are matched to the reflective characteristics of the radiation-blocking layer enables a reduction in critical dimension size and an improvement in the pattern feature integrity in the hard mask itself. An anti-reflective hard mask layer left on the radiation-blocking layer provides functionality when the reticle is used in a semiconductor device manufacturing process.

Abstract: A method of reactively sputtering from a metallic zinc target a transparent conductive oxide electrode of zinc oxide from a metallic zine in a silicon photo diode device and the resultant product, such as a solar cell. The electrode in deposited on a transparent substrate in at least two steps. The oxygen partial pressure is reduced in the first step to produce an oxygen-deficient ZnO layer, which is highly conductive and has a textured surface, and is increased in the second step to produce a more stoichiometric ZnO, which has a refractive index more closely matched to the overlying silicon device. The second layer is substantially thinner than the first so the surface texture is transferred across it and the overall sheet resistance of the stack structure is reduced.

Abstract: The present invention relates to semiconductor reaction chambers including a substrate support structure with rapid temperature change capabilities. The methods and components of the present invention may be used substrate deposition and related processes where varied temperatures are used. In accordance with the advantages of the present invention, the reaction chambers and substrate support structures of the invention can change temperature within a short duration of time, thereby allowing quicker processing times. The substrate support structures generally include a susceptor surface formed from a material having configured so as to allow for rapid temperature change of greater than about 10° C./sec.

Abstract: A datum plate is provided for use in installations of substrate handling systems. The datum plate has a set of predetermined attachment locations adapted to couple the datum plate to a chamber; a set of predetermined attachment locations adapted to couple one or more automatic door opener platforms to the datum plate; and a set of predetermined attachment locations adapted to couple one or more substrate handlers contained within the chamber, to the datum plate. The attachment locations are positioned such that when the datum plate is coupled to the chamber, and the automatic door opener platform and the substrate handler are coupled to the datum plate, the substrate handler and automatic door opener platform are aligned for substrate transfer therebetween. Numerous other aspects are provided.

Abstract: Embodiments of a method of calculating the equivalent series resistance of a matching network using variable impedance analysis and matching networks analyzed using the same are provided herein. In one embodiment, a method of calculating the equivalent series resistance of a matching network includes the steps of connecting the matching network to a load; measuring an output of the matching network over a range of load impedances; and calculating the equivalent series resistance of the matching network based upon a relationship between the measured output and the load resistance. The load may be a surrogate load or may be a plasma formed in a process chamber.

Abstract: An optical inspection system rapidly evaluates a substrate by illumination of an area of a substrate larger than a diffraction-limited spot using a coherent laser beam by breaking temporal or spatial coherence. Picosecond or femtosecond pulses from a modelocked laser source are split into a plurality of spatially separated beamlets that are temporally and/or frequency dispersed, and then focused onto a plurality of spots on the substrate. Adjacent spots, which can overlap by up to about 60-70 percent, are illuminated at different times, or at different frequencies, and do not produce mutually interfering coherence effects. Bright-field and dark-field detection schemes are used in various combinations in different embodiments of the system.

Abstract: In a first aspect, a substrate loading station is served by a conveyor which continuously transports substrate carriers. A substrate carrier handler that is part of the substrate loading station operates to exchange substrate carriers with the conveyor while the conveyor is in motion. A carrier exchange procedure may include moving an end effector of the substrate carrier handler at a velocity that substantially matches a velocity of the conveyor. Numerous other aspects are provided.

Abstract: A plasma reactor has a dual frequency plasma RF bias power supply furnishing RF bias power comprising first and second frequency components, f(1), f(2), respectively, and an RF power path having an input end coupled to the plasma RF bias power supply and an output end coupled to the wafer support pedestal, and sensor circuits providing measurement signals representing first and second frequency components of a measured voltage and first and second frequency components of a measured current near the input end of the RF power path. The reactor further includes a processor for providing first and second frequency components of a wafer voltage signal as, respectively, a first sum of the first frequency components of the measured voltage and measured current multiplied by first and second coefficients respectively, and a second sum of the second frequency components of the measured voltage and measured current multiplied by third and fourth coefficients, respectively. A processor produces a D.C.

Abstract: Embodiments of a cluster tool, processing chamber and method for processing a film stack are provided. In one embodiment, a method for in-situ etching of silicon and metal layers of a film stack is provided that includes the steps of etching an upper metal layer of the film stack in a processing chamber to expose a portion of an underlying silicon layer, and etching a trench in the silicon layer without removing the substrate from the processing chamber. The invention is particularly useful for thin film transistor fabrication for flat panel displays.

Abstract: Described herein are methods of forming a thin silicon dioxide layer having a thickness of less than eight angstroms on a semiconductor substrate to form the bottom layer of a gate dielectric. A silicon dioxide layer having a thickness of less than eight angstroms may be formed by two different methods. In one method, a sulfuric acid solution is applied to a semiconductor substrate to grow a silicon dioxide layer of less than eight angstroms. The growth of the silicon dioxide layer by the sulfuric acid solution is self-limiting. In another method, a hydrogen peroxide containing solution is applied to a semiconductor substrate for a time sufficient to grow a silicon dioxide layer having a thickness of greater than eight angstroms and then applying an etching solution to etch the silicon dioxide layer down to a thickness of less than eight angstroms.

Abstract: A plasma sputter chamber and process for sputtering ruthenium and tantalum at low pressure or with self-sustained sputtering (SSS). The source magnetron is strongly unbalanced and of sufficient size to project the unbalanced magnetic field toward the wafer to increase the ionization probability. Sputter etch uniformity is increased by the use of an auxiliary magnet system rotating with the source magnetron but placed towards the center of rotation. It may be a larger, nearly balanced auxiliary magnetron with an outer polarity matching that of the source magnetron or an array of magnets of that polarity. An integrated process includes a directional deposition of the refractory metal and its nitride, a sputter etch, and a flash deposition.

Abstract: A method and apparatus are provided for measuring the thickness of a test object. The apparatus includes an eddy current sensor having first and second sensor heads. The sensor heads are positioned to have a predetermined gap therebetween for passage by at least a portion of the test object through the gap. The sensor heads make measurements at given sampling locations on the test object as the test object is moved through the gap. The apparatus also includes a position sensing mechanism to determine positions of the sampling locations on the test object. The apparatus also includes an evaluation circuit in communication with the eddy current sensor and to the position sensing mechanism for determining the thickness of the test object at the sampling locations.

Abstract: A method for monitoring performance of an advanced process control system for at least one process output includes calculating a variance of a prediction error for a processing performance and/or a probability for violating specification limits of the processing performance of the at least one process output. If the variance of the prediction error is calculated, the method also includes calculating a model health index. If the probability for violating specification limits is calculated, the method further includes calculating a process health index.

Abstract: A polishing system can have a polishing pad with a polishing surface and a bottom surface that includes a recess with a thickness less than the thickness of the polishing pad. An in-situ monitoring module can be positioned in a cavity formed in part by the recess. A vent path is provided with an opening to the cavity.

Abstract: An improved prober for an electronic devices test system is provided. The prober is “configurable,” meaning that it can be adapted for different device layouts and substrate sizes. The prober generally includes a frame, at least one prober bar having a first end and a second end, a frame connection mechanism that allows for ready relocation of the prober bar to the frame at selected points along the frame, and a plurality of electrical contact pins along the prober bar for placing selected electronic devices in electrical communication with a system controller during testing. In one embodiment, the prober is be used to test devices such as thin film transistors on a glass substrate. Typically, the glass substrate is square, and the frame is also square. In this way, “x” and “y” axes are defined by the frame. The electrical pins may be movable along the axial length of the prober bars, or may be selectively pushed down to contact selected contact pads on the substrate.

Abstract: A CMOS gate stack that increases the inversion capacitance compared to a conventional CMOS gate stack has been described. Using a poly-SiGe gate, instead of the conventional poly-Si gate near the gate dielectric layer, increases the amount of implanted dopant that can be activated. This increase overcomes the polysilicon depletion problem that limits the inversion capacitance in the conventional CMOS gate stack. To integrate the poly-SiGe layer into the gate stack, a thin ?-Si layer is deposited between the gate dielectric layer and the poly-SiGe layer. To ensure proper salicide formation, a poly-Si layer is capped over the poly-SiGe layer. In order to obtain a fined-grained poly-Si over poly-SiGe, a second ?-Si layer is deposited between the poly-Si layer and the poly-SiGe layer.

Abstract: The present invention is directed to an upper chamber design of a plasma CVD chamber which provides more uniform conditions for forming thin CVD films on a substrate. Embodiments of the invention improve temperature control of the upper chamber and improve particle performance by reducing or minimizing the temperature fluctuations on the dome between the deposition and non-deposition cycles. In accordance with an aspect of the present invention, an apparatus for processing semiconductor substrates comprises a chamber defining a plasma processing region therein. The chamber includes a bottom, a side wall, and a dome disposed on top of the side wall. The dome has a substantially flat dome top. A top RF coil is disposed above the dome top, and has an outer loop which is larger in size than the substrates to be processed in the chamber. A cold plate is disposed above the top RF coil, and is larger in size than the substrates to be processed in the chamber.