Patents Assigned to Applied Material
-
Patent number: 7132338Abstract: In one embodiment, a method for fabricating a silicon-based device on a substrate surface is provided which includes depositing a first silicon-containing layer by exposing the substrate surface to a first process gas comprising Cl2SiH2, a germanium source, a first etchant and a carrier gas and depositing a second silicon-containing layer by exposing the first silicon-containing layer to a second process gas comprising SiH4 and a second etchant. In another embodiment, a method for depositing a silicon-containing material on a substrate surface is provided which includes depositing a first silicon-containing layer on the substrate surface with a first germanium concentration of about 15 at % or more.Type: GrantFiled: May 14, 2004Date of Patent: November 7, 2006Assignee: Applied Materials, Inc.Inventors: Arkadii V. Samoilov, Yihwan Kim, Errol Sanchez, Nicholas C. Dalida
-
Patent number: 7132369Abstract: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.Type: GrantFiled: December 22, 2003Date of Patent: November 7, 2006Assignee: Applied Materials, Inc.Inventors: Gerardo A. Delgadino, Yan Ye, Neungho Shin, Yunsang Kim, Li-Qun Xia, Tzu-Fang Huang, Lihua Li, Joey Chiu, Xiaoye Zhao, Fang Tian, Wen Zhu, Ellie Yieh
-
Patent number: 7132353Abstract: A method of forming a sidewall spacer on a gate electrode is described. The method includes generating a first plasma from a silicon containing precursor and oxide precursor, and forming a silicon oxy-nitride layer on the sidewall of the gate electrode. The method also includes generating a second plasma from the silicon containing precursor and a nitrogen precursor, and forming a nitride layer on the silicon oxy-nitride layer. The silicon containing precursor can flow continuously between the generation of the first and the second plasmas. Also, a method of forming a sidewall spacer on the side of a gate electrode on a substrate. The method includes forming an oxy-nitride layer on the sidewall, and forming a nitride layer on the oxy-nitride layer, where the substrate wafer is not exposed to air between the formation of the layers.Type: GrantFiled: August 2, 2005Date of Patent: November 7, 2006Assignee: Applied Materials, Inc.Inventors: Li-Qun Xia, Mei-Yee Shek, Troy Kim, Vladamir Zubkov, Ritwik Bhatia
-
Patent number: 7132134Abstract: A method and apparatus for depositing a conformal dielectric layer employing a dep-etch technique features selectively reducing the flow of deposition gases into a process chamber where a substrate having a stepped surface to be covered by the conformal dielectric layer is disposed. By selectively reducing the flow of deposition gases into the process chamber, the concentration of a sputtering gas, from which a plasma is formed, in the process chamber is increased without increasing the pressure therein. It is preferred that the flow of deposition gases be periodically terminated so as to provide a sputtering gas concentration approaching 100%. In this fashion, the etch rate of a conformal dielectric layer having adequate gap-filling characteristics may be greatly increased, while allowing an increase in the deposition rate of the same.Type: GrantFiled: September 10, 2004Date of Patent: November 7, 2006Assignee: Applied Materials, Inc.Inventor: Kent Rossman
-
Patent number: 7133549Abstract: A method and apparatus for inspecting a reticle measures line widths using an inspection tool that images the reticle and compares the image with a design database to detect errors in real time. The differences between the line widths of patterns on the reticle and the design database are stored during the inspection procedure. The difference (or “bias”) information is then processed off-line to create a map of all the local line-width deviation values (i.e., bias) of every feature on the reticle. The resultant local bias map can be used as a feedback mechanism to improve the reticle manufacturing process, as a “go/no go” criteria for the validity of the reticle, and as a standard report shipped together with the mask to the wafer fabrication facility, where it can be used as a yield-enhancing tool.Type: GrantFiled: December 19, 2002Date of Patent: November 7, 2006Assignee: Applied Materials, Inc.Inventors: Yair Eran, Gad Greenberg, Ami Sade, Shirley Hemar
-
Patent number: 7129440Abstract: Apparatus for thermally processing a semiconductor wafer includes an array of semiconductor laser emitters arranged in plural parallel rows extending along a slow axis, plural respective cylindrical lenses overlying respective ones of the rows of laser emitters for collimating light from the respective rows along a fast axis generally perpendicular to the slow axis, a homogenizing light pipe having an input face at a first end for receiving light from the plural cylindrical lenses and an output face at an opposite end, the light pipe comprising a pair of reflective walls extending between the input and output faces and separated from one another along the direction of the slow axis, and scanning apparatus for scanning light emitted from the homogenizing light pipe across the wafer in a scanning direction parallel to the fast axis.Type: GrantFiled: July 20, 2005Date of Patent: October 31, 2006Assignee: Applied Materials, Inc.Inventors: Bruce E. Adams, Dean Jennings, Abhilash J. Mayur, Vijay Parihar, Joseph M. Ranish
-
Patent number: 7128825Abstract: Polishing compositions and methods for removing conductive materials from a substrate surface are provided. In one aspect, a composition includes an acid based electrolyte system, one or more chelating agents, one or more corrosion inhibitors, one or more inorganic or organic acid salts, one or more pH adjusting agents to provide a pH between about 3 and about 10, a polishing enhancing material selected from the group of abrasive particles, one or more oxidizers, and combinations thereof, and a solvent. The composition may be used in an conductive material removal process including disposing a substrate having a conductive material layer formed thereon in a process apparatus comprising an electrode, providing the composition between the electrode and substrate, applying a bias between the electrode and the substrate, and removing conductive material from the conductive material layer.Type: GrantFiled: February 26, 2003Date of Patent: October 31, 2006Assignee: Applied Materials, Inc.Inventors: Feng Q. Liu, Stan D. Tsai, Yongqi Hu, Siew S. Neo, Yan Wang, Alain Duboust, Liang-Yuh Chen
-
Patent number: 7129694Abstract: A system and method for testing substrates is generally provided. In one embodiment, a test system for testing a substrate includes a load lock chamber, a transfer chamber and a test station. The load lock chamber and the test station are disposed on top of one another and coupled to the transfer chamber. The transfer chamber includes a robot adapted to transfer a substrate between the load lock chamber, which is at a first elevation, and the test station, which is at a second elevation. In another embodiment, a test station is provided having a turntable adapted to rotate the substrate. The turntable enables the range of motion required to test the substrate to be substantially reduced while facilitating full test and/or inspection of the substrate.Type: GrantFiled: May 23, 2002Date of Patent: October 31, 2006Assignee: Applied Materials, Inc.Inventors: Matthias Brunner, Shinichi Kurita, Wendell T. Blonigan, Edgar Kehrberg
-
Patent number: 7128823Abstract: Embodiments of the invention provide a method for plating copper into features formed on a semiconductor substrate. The method includes positioning the substrate in a plating cell, wherein the plating cell includes a catholyte volume containing a catholyte solution, an anolyte volume containing an anolyte solution, an ionic membrane positioned to separate the anolyte volume from the catholyte volume, and an anode positioned in the anolyte volume. The method further includes applying a plating bias between the anode and the substrate, plating copper ions onto the substrate from the catholyte solution, and replenishing the copper ions plated onto the substrate from the catholyte solution with copper ions transported from the anolyte solution via the ionic membrane, wherein the catholyte solution has a copper concentration of greater than about 51 g/L.Type: GrantFiled: July 8, 2003Date of Patent: October 31, 2006Assignee: Applied Materials, Inc.Inventors: Michael X. Yang, Nicolay Y. Kovarsky
-
Patent number: 7130055Abstract: A coefficient of a function that relates a measurement from a wafer to a parameter used in making the measurement (such as the power of a beam used in the measurement) is determined. The coefficient is used to evaluate the wafer (e.g. to accept or reject the wafer for further processing), and/or to control fabrication of another wafer. In one embodiment, the coefficient is used to control operation of a wafer processing unit (that may include, e.g. an ion implanter), or a heat treatment unit (such as a rapid thermal annealer).Type: GrantFiled: October 29, 2004Date of Patent: October 31, 2006Assignee: Applied Materials, Inc.Inventors: Peter G. Borden, Regina G. Nijmeijer, Beverly J. Klemme
-
Patent number: 7128806Abstract: Method and apparatus for supporting and transferring a substrate in a semiconductor wafer processing system are provided. In one aspect, an apparatus is provided for supporting a substrate comprising-a cover ring comprising a base having a bore disposed therethough, the base having an upper surface and one or more raised surfaces disposed adjacent the bore, wherein the raised surface comprise one or more first substrate support members disposed adjacent an edge of the bore and a capture ring disposed on the cover ring, the capture ring comprising a semi-circular annular ring having an inner perimeter corresponding to the bore of the cover ring and one or more second substrate support members disposed on the inner perimeter and adapted to receive a substrate, wherein the capture ring is adapted to mate with the cover ring and form one contiguous raised surface on the cover ring.Type: GrantFiled: October 21, 2003Date of Patent: October 31, 2006Assignee: Applied Materials, Inc.Inventors: Khiem Nguyen, Peter Satitpunwaycha, Alfred W. Mak
-
Publication number: 20060239605Abstract: An optoelectronic circuit including: an IC chip made up of a substrate in which an optical waveguide and a mirror have been fabricated, the substrate having a first lens formed thereon, wherein the mirror is aligned with the optical waveguide and the first lens is aligned with the mirror to form an optical path connecting the first lens, the mirror, and the optical waveguide; and an optical coupler including a second lens, the optical coupler affixed to the substrate and positioned to align the second lens with the first lens so as to couple an optical signal into or out of the optical waveguide within the IC chip.Type: ApplicationFiled: February 14, 2006Publication date: October 26, 2006Applicant: Applied Materials, Inc.Inventors: Edward Palen, Gregory Wojcik, Lawrence West
-
Publication number: 20060237432Abstract: An integrated thermal unit comprising a bake plate having a substrate holding surface configured to hold and heat a substrate in a baking position and a chill plate having a substrate holding surface configured to hold and cool a substrate in a cooling position where the substrate holding surface of the bake plate is positioned in a first substantially horizontal plane when the bake plate is in the baking position and the substrate holding surface of the chill plate is positioned in a second substantially horizontal plane that is below the first plane when the chill plate is in a cooling position.Type: ApplicationFiled: July 5, 2005Publication date: October 26, 2006Applicant: Applied Materials, Inc.Inventors: David Quach, Tetsuya Ishikawa
-
Publication number: 20060237431Abstract: An integrated thermal unit comprises a bake station comprising a bake plate configured to hold and heat a substrate; a chill station comprising a chill plate configured to hold and cool a substrate; and a substrate transfer shuttle configured to transfer substrates from the bake plate to the chill plate along a horizontally linear path within the thermal unit and raise and lower substrates along a vertical path within the integrated thermal unit.Type: ApplicationFiled: July 5, 2005Publication date: October 26, 2006Applicant: Applied Materials, Inc.Inventors: David Quach, Martin Salinas
-
Publication number: 20060237433Abstract: An integrated thermal unit comprising a bake plate configured to heat a substrate supported on a surface of the bake plate; a chill plate configured to cool a substrate supported on a surface of the chill plate; and a substrate transfer shuttle configured to transfer substrates from the bake plate to the cool plate, wherein the substrate transfer shuttle has a temperature controlled substrate holding surface that is capable of cooling a substrate heated by the bake plate.Type: ApplicationFiled: July 5, 2005Publication date: October 26, 2006Applicant: Applied Materials, Inc.,Inventors: David Quach, Martin Salinas
-
Publication number: 20060237430Abstract: A bake station comprising a bake plate adapted to heat a substrate supported on an upper surface of the bake plate, the bake plate vertically moveable between an upper baking position and a lower cooling position; and a plurality of heat sinks adapted to be engageably coupled to a lower surface of the bake plate when the bake plate is in the lower cooling position.Type: ApplicationFiled: July 5, 2005Publication date: October 26, 2006Applicant: Applied Materials, Inc.Inventors: David Quach, Tetsuya Ishikawa
-
Publication number: 20060238954Abstract: A chuck for a semiconductor workpiece features integrated resistive heating and electrostatic bipolar chucking elements on a thermal pedestal. These integrated heating and chucking elements maintain wafer flatness, as well as uniformity of an underlying gap accommodating a thermal gas between the workpiece and the chuck. In accordance with one embodiment of the present invention, a laminated Kapton wafer heater is attached to the top of the thermal surface, under the wafer: At least two electrical voltage zones are isolated within the heater, in order to create a chucking force between the chuck and the wafer without having to contact the wafer with an electrical conductor. These voltage zones can be created by using separate conducting elements as well as by imposing a DC bias on zones including the resistive heating elements.Type: ApplicationFiled: June 15, 2005Publication date: October 26, 2006Applicant: Applied Materials, Inc., A Delaware corporationInventors: Tetsuya Ishikawa, Brian Lue
-
Patent number: 7126138Abstract: An electron flood apparatus 1 of the present invention comprises a chamber 22 having a first part 22a made of conductive material and a second part 22b made of insulating material, and extending along a predefined closed curve Ax. A coil 18 is provided outside the first part 22a to generate a magnetic field in a direction intersecting with the surface formed by the predefined closed curve Ax. The coil 18 and the chamber 22 are inductively coupled by the magnetic field. Since the inert gas plasma is generated in the chamber 22 mainly by inductive coupling, electrons contained in the plasma have a low energy. Here, by applying voltage to an electrode 21, electrons having a low energy in the chamber 22 are emitted from an opening 14.Type: GrantFiled: September 16, 2004Date of Patent: October 24, 2006Assignee: Applied Materials, Inc.Inventors: Hiroyuki Ito, Yasuhiko Matsunaga, Hiroji Hanawa
-
Patent number: 7125477Abstract: Systems and methods for electrochemically processing. A contact element defines a substrate contact surface positionable in contact a substrate during processing. In one embodiment, the contact element comprises a wire element. In another embodiment the contact element is a rotating member. In one embodiment, the contact element comprises a noble metal.Type: GrantFiled: August 2, 2002Date of Patent: October 24, 2006Assignee: Applied Materials, Inc.Inventors: Paul Butterfield, Liang-Yuh Chen, Yongqi Hu, Antoine Manens, Rashid Mavliev, Stan Tsai
-
Patent number: 7125813Abstract: A method is provided for processing a substrate including providing a processing gas comprising an organosilicon compound comprising a phenyl group to the processing chamber, and reacting the processing gas to deposit a low k silicon carbide barrier layer useful as a barrier layer in damascene or dual damascene applications with low k dielectric materials.Type: GrantFiled: April 20, 2004Date of Patent: October 24, 2006Assignee: Applied Materials, Inc.Inventors: Li-Qun Xia, Ping Xu, Louis Yang
