Patents Assigned to Applied Material
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Patent number: 7115517Abstract: A method of fabricating an interconnect structure (e.g., dual damascene interconnect structure, and the like) of an integrated circuit device is disclosed. The interconnect structure is fabricated using a bi-layer mask comprising an imaging film and an organic planarizing film. The bi-layer mask is used to remove lithographic misalignment between a contact hole, a trench, and an underlying conductive line when the interconnect structure is formed. Additionally, a sacrificial layer may be used to protect an inter-metal dielectric (IMD) layer during subsequent planarization of the interconnect structure. The sacrificial layer may be formed of amorphous silicon (Si), titanium nitride (TiN), tungsten (W), and the like. The interconnect structure may be formed of a metal (e.g., copper (Cu), aluminum (Al), tantalum (Ti), tungsten (W), titanium (Ti), and the like) or a conductive compound (e.g., tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), and the like).Type: GrantFiled: September 29, 2003Date of Patent: October 3, 2006Assignee: Applied Materials, Inc.Inventors: Yan Ye, Xiaoye Zhao, Hong Du
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Patent number: 7115499Abstract: A method for depositing a tungsten nitride layer is provided. The method includes a cyclical process of alternately adsorbing a tungsten-containing compound and a nitrogen-containing compound on a substrate. The barrier layer has a reduced resistivity, lower concentration of fluorine, and can be deposited at any desired thickness, such as less than 100 angstroms, to minimize the amount of barrier layer material.Type: GrantFiled: December 1, 2004Date of Patent: October 3, 2006Assignee: Applied Materials, Inc.Inventors: Shulin Wang, Ulrich Kroemer, Lee Luo, Aihua Chen, Ming Li
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Patent number: 7114693Abstract: A stable platform supports a cell, the stable platform comprises a lower mainframe, an upper mainframe, and a dampener system. The upper mainframe includes a plurality of recesses. Each recess is configured to receive a cell. The dampener system connects the lower mainframe to the upper mainframe. In one embodiment, the dampener system comprises a dampener element, such as sand, to dampen vibrations between the lower mainframe and the lower mainframe.Type: GrantFiled: September 29, 2000Date of Patent: October 3, 2006Assignee: Applied Materials, Inc.Inventors: Donald J. K. Olgado, Timothy J. Franklin, Avi Tepman
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Patent number: 7115523Abstract: A process is provided for etching a silicon based material in a substrate, such as a photomask, to form features with straight sidewalls, flat bottoms, and high profile angles between the sidewalls and bottom, and minimizing the formation of polymer deposits on the substrate. In the etching process, the substrate is positioned in a processing chamber, a processing gas comprising a fluorocarbon, which advantageously is a hydrogen free fluorocarbon, is introduced into the processing chamber, wherein the substrate is maintained at a reduced temperature, and the processing gas is excited into a plasma state at a reduced power level to etch the silicon based material of the substrate. The processing gas may further comprise an inert gas, such as argon.Type: GrantFiled: March 18, 2003Date of Patent: October 3, 2006Assignee: Applied Materials, Inc.Inventors: Brigitte C. Stoehr, Michael D. Welch, Melisa J. Buie
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Patent number: 7115024Abstract: A platen for chemical mechanical polishing of a substrate includes a surface upon which a polishing pad can be placed, a support structure, and a controller. The surface has a first region and a second region and is operable to exert force against the polishing pad during polishing. The support structure is located beneath the second region and is operable to cause the second region to exert more force than the first region. The controller is operable to adjust the amount of force that is exerted by the second region.Type: GrantFiled: January 5, 2005Date of Patent: October 3, 2006Assignee: Applied Materials, Inc.Inventors: Hung Chih Chen, Steven M. Zuniga, Charles C. Garretson, Thomas H. Osterheld, Sen-Hou Ko, Mohsen Salek
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Patent number: 7115534Abstract: Methods are provided for depositing a dielectric material for use as an anti-reflective coating and sacrificial dielectric material in damascene formation. In one aspect, a process is provided for processing a substrate including depositing an acidic dielectric layer on the substrate by reacting an oxygen-containing organosilicon compound and an acidic compound, depositing a photoresist material on the acidic dielectric layer, and patterning the photoresist layer. The acidic dielectric layer may be used as a sacrificial layer in forming a feature definition by etching a partial feature definition, depositing the acidic dielectric material, etching the remainder of the feature definition, and then removing the acidic dielectric material to form a feature definition.Type: GrantFiled: May 18, 2004Date of Patent: October 3, 2006Assignee: Applied Materials, Inc.Inventors: Son Van Nguyen, Michael D. Armacost, Mehul Naik, Girish A. Dixit, Ellie Y. Yieh
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Patent number: 7115508Abstract: A method for seasoning a chamber and depositing a low dielectric constant layer on a substrate in the chamber is provided. In one aspect, the method includes seasoning the chamber with a first mixture comprising one or more organosilicon compounds and one or more oxidizing gases and depositing a low dielectric constant layer on a substrate in the chamber from a second mixture comprising one or more organosilicon compounds and one or more oxidizing gases, wherein a ratio of the total flow rate of the organosilicon compounds to the total flow rate of the oxidizing gases in the first mixture is lower than the total flow rate of the organosilicon compounds to the total flow rate of the oxidizing gases in the second mixture.Type: GrantFiled: April 2, 2004Date of Patent: October 3, 2006Assignee: Applied-Materials, Inc.Inventors: Sohyun Park, Wen H. Zhu, Tzu-Fang Huang, Li-Qun Xia, Hichem M'Saad
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Publication number: 20060216926Abstract: A method of fabricating an interconnect structure (e.g., dual damascene interconnect structure, and the like) of an integrated circuit device is disclosed. The interconnect structure is fabricated using a bi-layer mask comprising an imaging film and an organic planarizing film. The bi-layer mask is used to remove lithographic misalignment between a contact hole, a trench, and an underlying conductive line when the interconnect structure is formed. Additionally, a sacrificial layer may be used to protect an inter-metal dielectric (IMD) layer during subsequent planarization of the interconnect structure. The sacrificial layer may be formed of amorphous silicon (Si), titanium nitride (TiN), tungsten (W), and the like. The interconnect structure may be formed of a metal (e.g., copper (Cu), aluminum (Al), tantalum (Ti), tungsten (W), titanium (Ti), and the like) or a conductive compound (e.g., tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), and the like).Type: ApplicationFiled: June 12, 2006Publication date: September 28, 2006Applicant: Applied Materials, Inc.Inventors: Yan Ye, Xiaoye Zhao, Hong Du
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Patent number: 7112812Abstract: An apparatus, system and method for measuring a feature of a three-dimensional object, such as a wafer carrier, are provided. The apparatus is for use with an optical scanner and comprises a mounting structure adapted to be disposed on the scanner. The mounting structure has a calibration mark adapted to be read by the scanner and is adapted to position the object so that it is at a first pre-determined distance from the calibration mark. In one aspect of the present invention, the mounting structure further comprises an alignment surface adapted to abut the object. The alignment surface is disposed at a second pre-determined distance from the calibration mark. In another aspect of the present invention, the alignment surface is adapted to abut the object at a point spaced apart from the scanning surface.Type: GrantFiled: December 28, 2001Date of Patent: September 26, 2006Assignee: Applied Materials, Inc.Inventor: Ronald Vern Schauer
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Patent number: 7112960Abstract: An eddy current monitoring system may include an elongated core. One or more coils may be coupled with the elongated core for producing an oscillating magnetic field that may couple with one or more conductive regions on a wafer. The core may be translated relative to the wafer to provide improved resolution while maintaining sufficient signal strength. An eddy current monitoring system may include a DC-coupled marginal oscillator for producing an oscillating magnetic field at a resonant frequency, where the resonant frequency may change as a result of changes to one or more conductive regions. Eddy current monitoring systems may be used to enable real-time profile control.Type: GrantFiled: July 31, 2003Date of Patent: September 26, 2006Assignee: Applied Materials, Inc.Inventors: G. Laurie Miller, Boguslaw A. Swedek, Manoocher Birang
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Patent number: 7112119Abstract: A polishing pad, polishing system, method of making a polishing pad and method of using a polishing pad. The polishing pad includes a polishing layer having a polishing surface, a backing layer with an aperture and a first portion that is permeable to liquid, and a sealant that penetrates a second portion of the backing layer adjacent to and surrounding the aperture such that the second portion is substantially impermeable to liquid. The aperture is positioned below a substantially fluid-impermeable element.Type: GrantFiled: April 6, 2006Date of Patent: September 26, 2006Assignee: Applied Materials, Inc.Inventors: Bogdan Swedek, David J. Lischka, Jeffrey Drue David, Dominic J. Benvegnu
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Patent number: 7112541Abstract: A method of processing a substrate including depositing a low dielectric constant film comprising silicon, carbon, and oxygen on the substrate and depositing an oxide rich cap on the low dielectric constant film is provided. The low dielectric constant film is deposited from a gas mixture comprising an organosilicon compound and an oxidizing gas in the presence of RF power in a chamber. The RF power and a flow of the organosilicon compound and the oxidizing gas are continued in the chamber after the deposition of the low dielectric constant film at flow rates sufficient to deposit an oxide rich cap on the low dielectric constant film.Type: GrantFiled: May 6, 2004Date of Patent: September 26, 2006Assignee: Applied Materials, Inc.Inventors: Li-Qun Xia, Huiwen Xu, Derek R. Witty, Hichem M'Saad
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Patent number: 7112270Abstract: Method and apparatus for process control of electro-processes. The method includes electro-processing a wafer by the application of two or more biases and determining an amount of charge removed as a result of each bias, separately. In one embodiment, an endpoint is determined for each bias when the amount of charge removed for a bias substantially equals a respective target charge calculated for the bias.Type: GrantFiled: June 6, 2003Date of Patent: September 26, 2006Assignee: Applied Materials, Inc.Inventors: Antoine P. Manens, Alain Duboust, Siew S. Neo, Liang-Yuh Chen
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Patent number: 7112528Abstract: The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates selective chemical vapor deposition aluminum (CVD Al) via fill with a metal wire, preferably copper, formed within a barrier layer. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.Type: GrantFiled: February 13, 2003Date of Patent: September 26, 2006Assignee: Applied Materials, Inc.Inventors: Liang-Yuh Chen, Ted Guo, Roderick Craig Mosley, Fusen Chen
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Patent number: 7112763Abstract: A rapid thermal processing (RTP) system including a transmission pyrometer monitoring the temperature dependent absorption of the silicon wafer for radiation from the RTP lamps at a reduced power level. A look-up table is created relating unnormalized values of photodetector photocurrents with wafer and radiant lamp temperatures. A calibrating step measures the photocurrent with known wafer and lamp temperatures and all photocurrents measured thereafter are accordingly normalized. The transmission pyrometer may be used for closed loop control for thermal treatments below 500° C. or used in the pre-heating phase for a higher temperature process including radiation pyrometry in closed loop control. The pre-heating temperature ramp rate may be controlled by measuring the initial ramp rate and readjusting the lamp power accordingly. Radiation and transmission pyrometers may be included in an integrated structure with a beam splitter dividing radiation from the wafer.Type: GrantFiled: October 26, 2004Date of Patent: September 26, 2006Assignee: Applied Materials, Inc.Inventors: Aaron Hunter, Rajesh S. Ramanujam, Balasubramanian Ramachandran, Corina Elena Tanasa, Tarpan Dixit
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Patent number: 7112803Abstract: A method and system are presented for directing a charged particle beam towards and away from a sample. The system comprises a lens arrangement having an electrode formed with a beam opening for a charged particle beam passage therethrough; and a magnetic deflector. The magnetic deflector has a magnetic circuit formed by a core part for carrying excitation coils and a polepieces part. The polepieces of the magnetic deflector are in electrical communication with the electrode of the lens arrangement and are electrically insulated from the other part of the magnetic circuit.Type: GrantFiled: July 23, 2004Date of Patent: September 26, 2006Assignee: Applied Materials, Israel, Ltd.Inventors: Igor Petrov, Igor Krivts (Krayvitz), Albert Karabekov
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Patent number: 7112961Abstract: A method and apparatus are provided for measuring the thickness of a test object. The apparatus includes an eddy current sensor having first and second sensor heads. The sensor heads are positioned to have a predetermined gap therebetween for passage by at least a portion of the test object through the gap. The sensor heads make measurements at given sampling locations on the test object as the test object is moved through the gap. The apparatus also includes a position sensing mechanism to determine positions of the sampling locations on the test object. The apparatus also includes an evaluation circuit in communication with the eddy current sensor and to the position sensing mechanism for determining the thickness of the test object at the sampling locations.Type: GrantFiled: October 14, 2003Date of Patent: September 26, 2006Assignee: Applied Materials, Inc.Inventors: Lawrence C. Lei, Siqing Lu, Yu Chang, Cecilia Martner, Quyen Pham, Yu Ping Gu, Joel Huston, Paul Smith, Gabriel Lorimer Miller
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Publication number: 20060207294Abstract: Embodiments of the present invention provide a highly uniform low cost production worthy solution for manufacturing low propagation loss optical waveguides on a substrate. In one embodiment, the present invention provides a method of forming a PSG optical waveguide on an undercladding layer of a substrate that includes forming at least one silicate glass optical core on said undercladding layer using a plasma enhanced chemical vapor deposition process including a silicon source gas, an oxygen source gas, and a phosphorus source gas, wherein the oxygen source gas and silicon source gas have a ratio of oxygen atoms to silicon atoms greater than 20:1.Type: ApplicationFiled: June 5, 2006Publication date: September 21, 2006Applicant: Applied Materials, Inc.Inventors: Hichem M'Saad, Anchuan Wang, Sang Ahn
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Patent number: 7110629Abstract: An article of manufacture comprising an optical-ready substrate made of a first semiconductor layer, an insulating layer on top of the first semiconductor layer, and a second semiconductor layer on top of the insulating layer, wherein the second semiconductor layer has a top surface and is laterally divided into two regions including a first region and a second region, the top surface of the first region being of a quality that is sufficient to permit microelectronic circuitry to be formed therein and the second region including an optical signal distribution circuit formed therein, the optical signal distribution circuit made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuit to be fabricated in the first region of the second semiconductor layer.Type: GrantFiled: July 21, 2003Date of Patent: September 19, 2006Assignee: Applied Materials, Inc.Inventors: Claes Bjorkman, Lawrence C. West, Dan Maydan, Samuel Broydo
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Patent number: 7109114Abstract: A method of operating a substrate processing chamber that includes, prior to a substrate processing operation, flowing a seasoning gas comprising silane and oxygen into said chamber at a flow ratio of greater than or equal to about 1.6:1 oxygen to silane to deposit a silicon oxide film over at least one aluminum nitride nozzle exposed to an interior portion of the chamber. Also, a substrate processing system that includes a housing, a gas delivery system for introducing a seasoning gas into a vacuum chamber, where the gas delivery system comprises one or more aluminum nitride nozzles exposed to the vacuum chamber, a controller and a memory having a program having instructions for controlling the gas delivery system to flow a seasoning gas that has an oxygen to silane ratio greater than or equal to about 1.6:1 to deposit a silicon oxide film on the aluminum nitride nozzles.Type: GrantFiled: May 7, 2004Date of Patent: September 19, 2006Assignee: Applied Materials, Inc.Inventors: Xiaolin Chen, Jason Bloking