Abstract: Mass flow verification systems and apparatus may verify mass flow rates of mass flow controllers (MFCs) based on choked flow principles. These systems and apparatus may include a plurality of differently-sized flow restrictors coupled in parallel. A wide range of flow rates may be verified via selection of a flow path through one of the flow restrictors based on an MFC's set point. Mass flow rates may be determined via pressure and temperature measurements upstream of the flow restrictors under choked flow conditions. Methods of verifying a mass flow rate based on choked flow principles are also provided, as are other aspects.

Abstract: The present disclosure relates to thin-form-factor semiconductor packages with integrated electromagnetic interference (“EMI”) shields and methods for forming the same. The packages described herein may be utilized to form high-density semiconductor devices. In certain embodiments, a silicon substrate is laser ablated to include one or more cavities and a plurality of vias surrounding the cavities. One or more semiconductor dies may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. A plurality of conductive interconnections are formed within the vias and may have contact points redistributed to desired surfaces of the die-embedded substrate assembly. Thereafter, an EMI shield is plated onto a surface of the die-embedded substrate assembly and connected to ground by at least one of the one or more conductive interconnections. The die-embedded substrate assembly may then be singulated and/or integrated with another semiconductor device.

Abstract: An additive manufacturing apparatus includes a platform, a dispenser configured to deliver a plurality of successive layers of feed material onto the platform, at least one light source configured to generate a first light beam and a second light beam, a polygon mirror scanner, an actuator, and a galvo mirror scanner. The polygon mirror scanner is configured to receive the first light beam and reflect the first light beam towards the platform. Rotation of the first polygon mirror causes the light beam to move in a first direction along a path on a layer of feed material on the platform. The actuator is configured to cause the path to move along a second direction at a non-zero angle relative to the first direction. The galvo mirror scanner system is configured to receive the second light beam and reflect the second light beam toward the platform.

Abstract: Embodiments disclosed herein include a method of calibrating a processing chamber. In an embodiment, the method comprises placing a sensor wafer onto a support surface in the processing chamber, wherein a process kit displaceable in the Z-direction is positioned around the support surface. In an embodiment, the method further comprises measuring a first gap distance between the sensor wafer and the process kit with a sensor on an edge surface of the sensor wafer. In an embodiment, the method further comprises displacing the process kit in the Z-direction. In an embodiment, the method further comprises measuring an additional gap distance between the sensor wafer and the process kit.

Abstract: One example of the disclosure provides a method of fabricating a chamber component with a coating comprising a yttrium containing material with desired film properties. In one example, the method of fabricating a coating material includes providing a base structure comprising an aluminum containing material. The method further includes forming a coating layer that includes a yttrium containing material on the base structure. The method also includes thermal treating the coating layer to form a treated coating layer.

Abstract: Embodiments disclosed herein generally include annealing chambers. The annealing chambers allow for high throughput without sacrificing wafer-to-wafer and within wafer uniformity. The annealing chamber includes a transport system, a substrate carrier, and a plurality of thermal sources. The transport system is magnetically coupled to the substrate carrier. The transport system moves the substrate carrier along a path. A substrate supported by the substrate carrier is annealed by the thermal sources. The annealing chamber described herein allows for a higher throughput of substrate (alternatively referred to as a wafer) annealing compared to furnace annealing chambers.

Abstract: Embodiments of the present disclosure provide methods and apparatus for forming a desired material layer on a substrate between, during, prior to or after a patterning process. In one embodiment, a method for forming a material layer on a substrate includes pulsing a first gas precursor onto a surface of a substrate, attaching a first element from the first gas precursor onto the surface of the substrate, maintaining a substrate temperature less than about 110 degrees Celsius, pulsing a second gas precursor onto the surface of the substrate, and attaching a second element from the second gas precursor to the first element on the surface of the substrate.

Abstract: Embodiments of the present invention provide apparatus, systems and methods for measuring dissociation of a process gas generated by a RPS. In one embodiment, a method of measuring dissociation of a process gas includes receiving a process gas from a RPS, the process gas including a polyatomic molecule that dissociates into at least one free radical. The method further includes irradiating the process gas with IR radiation at one or more wavelengths, detecting the IR radiation that passes through the process gas, and determining a degree of dissociation of the polyatomic molecule in the process gas based, at least in part, on the detected IR radiation. In one embodiment, the method further comprises modifying one or more settings of the RPS, based, at least in part, on the determined degree of dissociation.

Abstract: The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.

Abstract: Disclosed herein is a method for depth-profiling of samples including a target region including a lateral structural feature. The method includes obtaining measured signals of the sample and analyzing thereof to obtain a depth-dependence of at least one parameter characterizing the lateral structural feature. The measured signals are obtained by repeatedly: projecting a pump pulse on the sample, thereby producing an acoustic pulse propagating within the target region; Brillouin-scattering a probe pulse off the acoustic pulse within the target region; and detecting a scattered component of the probe pulse to obtain a measured signal. In each repetition the respective probe pulse is scattered off the acoustic pulse at a respective depth within the target region, thereby probing the target region at a plurality of depths. A wavelength of the pump pulse is at least about two times greater than a lateral extent of the lateral structural feature.

Abstract: Methods of enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a dielectric. In some embodiments, a metal surface is functionalized to enhance or decrease its reactivity.

Abstract: Exemplary methods of treating a chamber may include delivering a cleaning precursor to a remote plasma unit. The methods may include forming a plasma of the cleaning precursor. The methods may include delivering plasma effluents of the cleaning precursor to a processing region of a semiconductor processing chamber. The processing region may be defined by one or more chamber components. The one or more chamber components may include an oxide coating. The methods may include halting delivery of the plasma effluents. The methods may include treating the oxide coating with a hydrogen-containing material delivered to the processing region subsequent halting delivery of the plasma effluents.

Abstract: Exemplary deposition methods may include delivering a boron-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the boron-containing precursor and the nitrogen-containing precursor. A flow rate ratio of the hydrogen-containing precursor to either of the boron-containing precursor or the nitrogen-containing precursor may be greater than or about 2:1. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a boron-and-nitrogen material on a substrate disposed within the processing region of the semiconductor processing chamber.

Abstract: A substrate holder assembly including a substrate platen, the substrate platen disposed to support a substrate at a substrate position, a halo ring, the halo ring being disposed around the substrate position, and an outer halo being disposed around the halo ring and defining a first aperture, wherein the outer halo is disposed to engage the halo ring, the halo ring being disposed at least partially within the first aperture, the halo ring defining a second aperture, concentrically positioned within the first aperture, wherein the outer halo and the halo ring are formed at least partially of silicon, silicon carbide, doped silicon, quartz, and ceramic.

Abstract: A method of inducing sparsity for outputs of neural network layer may include receiving outputs from a layer of a neural network; partitioning the outputs into a plurality of partitions; identifying first partitions in the plurality of partitions that can be treated as having zero values; generating an encoding that identifies locations of the first partitions among remaining second partitions in the plurality of partitions; and sending the encoding and the second partitions to a subsequent layer in the neural network.

Abstract: A memory device comprises: a stack of alternating silicon oxide layers and wordline layers; each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal. The dipole regions are formed by driving a dipole film into a gate oxide layer of the wordline layers, and any residual dipole film is removed.

Abstract: Wafers that begin as flat surfaces during a semiconductor manufacturing process may become warped or bowed as layers and features are added to an underlying substrate. This warpage may be detected between manufacturing processes by rotating the wafer adjacent to a displacement sensor. The displacement sensor may generate displacement data relative to a baseline measurement to identify areas of the wafer that bow up or down. The displacement data may then be mapped to locations on the wafer relative to an alignment feature. This mapping may then be used to adjust parameters in subsequent semiconductor processes, including adjusting how a carrier head on a polishing process holds or applies pressure to the wafer as it is polished.

Abstract: Wafers that begin as flat surfaces during a semiconductor manufacturing process may become warped or bowed as layers and features are added to an underlying substrate. This warpage may be detected between manufacturing processes by rotating the wafer adjacent to a displacement sensor. The displacement sensor may generate displacement data relative to a baseline measurement to identify areas of the wafer that bow up or down. The displacement data may then be mapped to locations on the wafer relative to an alignment feature. This mapping may then be used to adjust parameters in subsequent semiconductor processes, including adjusting how a carrier head on a polishing process holds or applies pressure to the wafer as it is polished. A model may be trained to provide control signals for a polishing/cleaning process, or to generate metrology data.

Abstract: A deposition method demonstrating a slower growth rate is disclosed. Some embodiments of the disclosure provide CVD methods which utilize a halide-containing growth inhibitor as a co-reactant with a metal halide precursor and a reactant. Some embodiments of the disclosure relate to CVD and ALD methods comprising exposure of the substrate surface to a pretreatment comprising a halide-containing growth inhibitor.

Abstract: Exemplary deposition methods may include delivering a ruthenium-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. At least one of the ruthenium-containing precursor or the hydrogen-containing precursor may include carbon. The methods may include forming a plasma of all precursors within the processing region of a semiconductor processing chamber. The methods may include depositing a ruthenium-and-carbon material on a substrate disposed within the processing region of the semiconductor processing chamber.